bdb3fc96d6
Wrapper is neccesary for the address offset and also because the controller will trigger on reads/writes to registers, but we need access to each byte of the 32 bit registers. The wrapper will need to somehow chose when to actually trigger the controller, maybe by having shadow registers?
19 lines
729 B
Plaintext
19 lines
729 B
Plaintext
[submodule "hw/super6502_fpga/src/sub/rtl-common"]
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path = hw/super6502_fpga/src/sub/rtl-common
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url = ../rtl-common.git
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[submodule "sw/toolchain/cc65"]
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path = sw/toolchain/cc65
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url = ../cc65.git
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[submodule "hw/super6502_fpga/src/sim/sub/verilog-6502"]
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path = hw/super6502_fpga/src/sim/sub/verilog-6502
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url = ../verilog-6502.git
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[submodule "hw/super6502_fpga/src/sim/sub/verilog-sd-emulator"]
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path = hw/super6502_fpga/src/sim/sub/verilog-sd-emulator
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url = ../verilog-sd-emulator.git
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[submodule "hw/super6502_fpga/src/sub/wb2axip"]
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path = hw/super6502_fpga/src/sub/wb2axip
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url = ../wb2axip.git
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[submodule "hw/super6502_fpga/src/sub/sdspi"]
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path = hw/super6502_fpga/src/sub/sd_controller_wrapper/sdspi
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url = ../sdspi.git
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