bdb3fc96d6
Wrapper is neccesary for the address offset and also because the controller will trigger on reads/writes to registers, but we need access to each byte of the 32 bit registers. The wrapper will need to somehow chose when to actually trigger the controller, maybe by having shadow registers?
32 lines
1.4 KiB
Plaintext
32 lines
1.4 KiB
Plaintext
src/rtl/super_6502_fpga.sv
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src/sub/cpu_wrapper/cpu_wrapper.sv
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src/sub/rtl-common/src/rtl/async_fifo.sv
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src/sub/rtl-common/src/rtl/axi4_lite_ram.sv
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src/sub/rtl-common/src/rtl/axi4_lite_rom.sv
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src/sub/rtl-common/src/rtl/ff_cdc.sv
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src/sub/rtl-common/src/rtl/shallow_async_fifo.sv
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src/sub/rtl-common/src/rtl/sync_fifo.sv
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src/sub/rtl-common/src/rtl/axi4_lite_to_apb4.sv
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ip/sdram_controller/sdram_controller.v
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src/sub/wb2axip/rtl/axilxbar.v
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src/sub/wb2axip/rtl/addrdecode.v
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src/sub/wb2axip/rtl/skidbuffer.v
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src/sub/sd_controller_wrapper/sd_controller_wrapper.sv
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src/sub/sd_controller_wrapper/sdspi/rtl/sdckgen.v
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src/sub/sd_controller_wrapper/sdspi/rtl/sddma_rxgears.v
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src/sub/sd_controller_wrapper/sdspi/rtl/sddma.v
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src/sub/sd_controller_wrapper/sdspi/rtl/sdrxframe.v
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src/sub/sd_controller_wrapper/sdspi/rtl/sdtxframe.v
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src/sub/sd_controller_wrapper/sdspi/rtl/sddma_s2mm.v
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src/sub/sd_controller_wrapper/sdspi/rtl/afifo.v
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src/sub/sd_controller_wrapper/sdspi/rtl/sddma_txgears.v
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src/sub/sd_controller_wrapper/sdspi/rtl/sdskid.v
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src/sub/sd_controller_wrapper/sdspi/rtl/sdfrontend.v
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src/sub/sd_controller_wrapper/sdspi/rtl/spicmd.v
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src/sub/sd_controller_wrapper/sdspi/rtl/sdaxil.v
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src/sub/sd_controller_wrapper/sdspi/rtl/sddma_mm2s.v
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src/sub/sd_controller_wrapper/sdspi/rtl/sdio_top.v
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src/sub/sd_controller_wrapper/sdspi/rtl/sdwb.v
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src/sub/sd_controller_wrapper/sdspi/rtl/sdio.v
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src/sub/sd_controller_wrapper/sdspi/rtl/sdcmd.v
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src/sub/sd_controller_wrapper/sdspi/rtl/sdfifo.v |