33 lines
576 B
Systemverilog
33 lines
576 B
Systemverilog
module testbench();
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timeunit 10ns;
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timeprecision 1ns;
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logic [15:0] addr;
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logic ram_cs;
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logic rom_cs;
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addr_decode dut(.*);
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initial begin : TEST_VECTORS
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for (int i = 0; i < 2**16; i++) begin
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addr <= i;
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#1
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if (i < 2**15) begin
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assert(ram_cs == '1)
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else
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$error("Bad CS! addr=%4x should have ram_cs!", addr);
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end
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if (i >= 2**15) begin
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assert(rom_cs == '1)
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else
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$error("Bad CS! addr=%4x should have rom_cs!", addr);
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end
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end
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end
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endmodule
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