Files
super6502/hw/fpga/simulation/modelsim/cs_testbench.do
2022-03-05 20:11:47 -06:00

23 lines
582 B
Plaintext

transcript on
if {[file exists rtl_work]} {
vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work
vlog -sv -work work {../../addr_decode.sv}
vlog -sv -work work {../../hvl/cs_testbench.sv}
vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L stratixv_ver -L stratixv_hssi_ver -L stratixv_pcie_hip_ver -L rtl_work -L work -voptargs="+acc" testbench
onfinish stop
run -all
if { [coverage attribute -name TESTSTATUS -concise] == "1"} {
echo Warning
quit -f -code 0
}
quit -code [coverage attribute -name TESTSTATUS -concise]