43 lines
886 B
Systemverilog
43 lines
886 B
Systemverilog
module SevenSeg(
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input clk,
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input rst,
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input rw,
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input [7:0] data,
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input cs,
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input [1:0] addr,
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output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5
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);
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logic [7:0] _data [3:0];
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always_ff @(posedge clk) begin
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if (rst)
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_data = '{default:'0};
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if (~rw & cs)
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_data[addr] <= data;
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end
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logic [3:0] hex_4[5:0];
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assign {hex_4[5], hex_4[4]} = _data[2];
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assign {hex_4[3], hex_4[2]} = _data[1];
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assign {hex_4[1], hex_4[0]} = _data[0];
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logic [6:0] _HEX0, _HEX1, _HEX2, _HEX3, _HEX4, _HEX5;
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HexDriver hex_drivers[5:0] (hex_4, {_HEX5, _HEX4, _HEX3, _HEX2, _HEX1, _HEX0});
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assign HEX0 = _HEX0 | {7{~_data[3][0]}};
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assign HEX1 = _HEX1 | {7{~_data[3][1]}};
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assign HEX2 = _HEX2 | {7{~_data[3][2]}};
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assign HEX3 = _HEX3 | {7{~_data[3][3]}};
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assign HEX4 = _HEX4 | {7{~_data[3][4]}};
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assign HEX5 = _HEX5 | {7{~_data[3][5]}};
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endmodule
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