bslathi19/super6502
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ca4288df66df9f03770a233914572b5be65b4818
super6502/hw/fpga
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Byron Lathi ca4288df66 Change addr_decode test to use new io locations 
Instead of whatever was there before, the new io locations are ram, rom,
and the hex digits.
2022-03-12 19:25:34 -06:00
..
greybox_tmp
Get the FPGA part working
2022-03-11 22:55:26 -06:00
hvl
Change addr_decode test to use new io locations
2022-03-12 19:25:34 -06:00
output_files
Get the FPGA part working
2022-03-11 22:55:26 -06:00
simulation/modelsim
Get the FPGA part working
2022-03-11 22:55:26 -06:00
.gitignore
Create quartus project
2022-03-05 16:38:12 -06:00
addr_decode.sv
Add hex drivers
2022-03-11 18:25:55 -06:00
bb_spi_controller.sv
Add bb_spi_controller
2022-03-08 15:26:01 -06:00
cpu_clk.ppf
Add hex drivers
2022-03-11 18:25:55 -06:00
cpu_clk.qip
Add hex drivers
2022-03-11 18:25:55 -06:00
cpu_clk.v
Add hex drivers
2022-03-11 18:25:55 -06:00
HexDriver.sv
Add hex drivers
2022-03-11 18:25:55 -06:00
ram.qip
Create quartus project
2022-03-05 17:52:42 -06:00
ram.v
Create quartus project
2022-03-05 17:52:42 -06:00
rom.qip
Add boot rom
2022-03-05 18:12:27 -06:00
rom.v
Get the FPGA part working
2022-03-11 22:55:26 -06:00
SevenSeg.sv
Get the FPGA part working
2022-03-11 22:55:26 -06:00
super6502.qpf
Create quartus project
2022-03-05 16:38:12 -06:00
super6502.qsf
Get the FPGA part working
2022-03-11 22:55:26 -06:00
super6502.sdc
Get the FPGA part working
2022-03-11 22:55:26 -06:00
super6502.sv
Get the FPGA part working
2022-03-11 22:55:26 -06:00