Files
super6502/hw/fpga/cpu_clk.ppf
2022-03-11 18:25:55 -06:00

10 lines
342 B
XML

<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="MAX 10" variation_name="cpu_clk" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
</global>
</pinplan>