118 lines
2.3 KiB
Systemverilog
118 lines
2.3 KiB
Systemverilog
`timescale 1ns/1ps
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module rtc_tb();
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logic r_clk_cpu;
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initial begin
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r_clk_cpu <= '1;
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forever begin
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#125 r_clk_cpu <= ~r_clk_cpu;
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end
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end
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logic reset, rwb, cs, addr, irq;
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logic [7:0] i_data, o_data;
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rtc u_rtc(
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.clk(r_clk_cpu),
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.reset(reset),
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.rwb(rwb),
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.cs(cs),
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.addr(addr),
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.i_data(i_data),
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.o_data(o_data),
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.irq(irq)
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);
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initial begin
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do_reset();
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set_increment(1);
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set_threshold(7);
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set_irq_threshold(2);
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enable_rtc(3);
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repeat (20) @(posedge r_clk_cpu);
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$finish();
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end
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initial begin
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$dumpfile("rtc_tb.vcd");
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$dumpvars(0,rtc_tb);
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end
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task do_reset();
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repeat (5) @(posedge r_clk_cpu);
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reset = 1;
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cs = 0;
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rwb = 1;
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addr = '0;
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i_data = '0;
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repeat (5) @(posedge r_clk_cpu);
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reset = 0;
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repeat (5) @(posedge r_clk_cpu);
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endtask
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/* These should be shared */
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task write_reg(input logic [4:0] _addr, input logic [7:0] _data);
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@(negedge r_clk_cpu);
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cs <= '1;
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addr <= _addr;
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rwb <= '0;
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i_data <= '1;
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@(posedge r_clk_cpu);
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i_data <= _data;
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@(negedge r_clk_cpu);
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cs <= '0;
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rwb <= '1;
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@(posedge r_clk_cpu);
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endtask
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task read_reg(input logic [2:0] _addr, output logic [7:0] _data);
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@(negedge r_clk_cpu);
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cs <= '1;
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addr <= _addr;
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rwb <= '1;
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i_data <= '1;
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@(posedge r_clk_cpu);
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_data <= o_data;
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@(negedge r_clk_cpu);
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cs <= '0;
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rwb <= '1;
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@(posedge r_clk_cpu);
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endtask
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task set_increment(input logic [31:0] _increment);
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for (int i = 0; i < 4; i++) begin
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write_reg(0, 8'h10 | i);
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write_reg(1, _increment[8*i +: 8]);
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end
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endtask
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task set_threshold(input logic [31:0] _threshold);
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for (int i = 0; i < 4; i++) begin
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write_reg(0, 8'h00 | i);
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write_reg(1, _threshold[8*i +: 8]);
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end
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endtask
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task set_irq_threshold(input logic [31:0] _increment);
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for (int i = 0; i < 4; i++) begin
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write_reg(0, 8'h20 | i);
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write_reg(1, _increment[8*i +: 8]);
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end
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endtask
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task enable_rtc(input logic [7:0] _ctrl);
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write_reg(0, 8'h30);
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write_reg(1, _ctrl);
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endtask
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task read_output(output logic [31:0] _output);
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for (int i = 0; i < 4; i++) begin
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write_reg(0, 8'h30 | i);
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read_reg(1, _output[8*i +: 8]);
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end
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endtask
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endmodule
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