221 lines
8.7 KiB
VHDL
221 lines
8.7 KiB
VHDL
--------------------------------------------------------------------------------
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-- Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
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--
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-- This document contains proprietary information which is
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-- protected by copyright. All rights are reserved. This notice
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-- refers to original work by Efinix, Inc. which may be derivitive
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-- of other work distributed under license of the authors. In the
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-- case of derivative work, nothing in this notice overrides the
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-- original author's license agreement. Where applicable, the
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-- original license agreement is included in it's original
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-- unmodified form immediately below this header.
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--
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-- WARRANTY DISCLAIMER.
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-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
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-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
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-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
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-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
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-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
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-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
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-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
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--
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-- LIMITATION OF LIABILITY.
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-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
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-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
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-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
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-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
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-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
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-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
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-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
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-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
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-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
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-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
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-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
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-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
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-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
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-- APPLY TO LICENSEE.
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--
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--------------------------------------------------------------------------------
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------------- Begin Cut here for COMPONENT Declaration ------
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COMPONENT sdram_controller is
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PORT (
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i_aresetn : in std_logic;
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i_AXI4_AWADDR : in std_logic_vector(23 downto 0);
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i_sysclk : in std_logic;
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i_sdrclk : in std_logic;
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i_tACclk : in std_logic;
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i_pll_locked : in std_logic;
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o_dbg_ref_req : out std_logic;
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o_dbg_wr_ack : out std_logic;
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o_dbg_rd_ack : out std_logic;
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o_dbg_n_CS : out std_logic_vector(1 downto 0);
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o_dbg_n_RAS : out std_logic_vector(1 downto 0);
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o_dbg_n_CAS : out std_logic_vector(1 downto 0);
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o_dbg_n_WE : out std_logic_vector(1 downto 0);
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o_dbg_BA : out std_logic_vector(3 downto 0);
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o_dbg_ADDR : out std_logic_vector(25 downto 0);
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o_dbg_DATA_out : out std_logic_vector(31 downto 0);
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o_dbg_DATA_in : out std_logic_vector(31 downto 0);
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o_pll_reset : out std_logic;
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o_AXI4_AWREADY : out std_logic;
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i_AXI4_AWVALID : in std_logic;
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o_AXI4_WREADY : out std_logic;
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i_AXI4_WDATA : in std_logic_vector(31 downto 0);
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i_AXI4_WSTRB : in std_logic_vector(3 downto 0);
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i_AXI4_WLAST : in std_logic;
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i_AXI4_WVALID : in std_logic;
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o_AXI4_BVALID : out std_logic;
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i_AXI4_BREADY : in std_logic;
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o_AXI4_ARREADY : out std_logic;
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i_AXI4_ARADDR : in std_logic_vector(23 downto 0);
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i_AXI4_RREADY : in std_logic;
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o_AXI4_RDATA : out std_logic_vector(31 downto 0);
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o_AXI4_RLAST : out std_logic;
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o_AXI4_RVALID : out std_logic;
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i_AXI4_AWID : in std_logic_vector(3 downto 0);
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i_AXI4_AWSIZE : in std_logic_vector(2 downto 0);
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i_AXI4_ARVALID : in std_logic;
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i_AXI4_ARID : in std_logic_vector(3 downto 0);
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i_AXI4_ARLEN : in std_logic_vector(7 downto 0);
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i_AXI4_ARSIZE : in std_logic_vector(2 downto 0);
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i_AXI4_ARBURST : in std_logic_vector(1 downto 0);
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i_AXI4_AWLEN : in std_logic_vector(7 downto 0);
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o_AXI4_RID : out std_logic_vector(3 downto 0);
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o_dbg_we : out std_logic;
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o_dbg_last : out std_logic;
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o_dbg_addr : out std_logic_vector(23 downto 0);
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o_dbg_din : out std_logic_vector(31 downto 0);
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o_axi4_wrstate : out std_logic_vector(1 downto 0);
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o_fifo_wr : out std_logic;
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o_fifo_full : out std_logic;
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o_fifo_empty : out std_logic;
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o_dbg_fifo_waddr : out std_logic_vector(7 downto 0);
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o_dbg_fifo_re : out std_logic;
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o_dbg_fifo_raddr : out std_logic_vector(7 downto 0);
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o_dbg_fifo_we : out std_logic;
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o_dbg_axi4_wlast : out std_logic;
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o_shift_cnt : out std_logic_vector(6 downto 0);
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o_re_lock : out std_logic;
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o_axi4_rastate : out std_logic_vector(1 downto 0);
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o_axi4_nwr : out std_logic;
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o_axi4_arlen : out std_logic_vector(7 downto 0);
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o_axi4_rdstate : out std_logic_vector(1 downto 0);
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o_sdr_rd_valid : out std_logic;
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o_sdr_dout : out std_logic_vector(36 downto 0);
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o_dbg_re : out std_logic;
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o_AXI4_BID : out std_logic_vector(3 downto 0);
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i_addr : in std_logic_vector(23 downto 0);
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i_din : in std_logic_vector(31 downto 0);
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i_dm : in std_logic_vector(3 downto 0);
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o_dout : out std_logic_vector(31 downto 0);
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o_sdr_state : out std_logic_vector(3 downto 0);
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o_sdr_init_done : out std_logic;
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o_wr_ack : out std_logic;
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o_rd_ack : out std_logic;
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o_ref_req : out std_logic;
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o_rd_valid : out std_logic;
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o_sdr_CKE : out std_logic_vector(1 downto 0);
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o_sdr_n_CS : out std_logic_vector(1 downto 0);
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o_sdr_n_RAS : out std_logic_vector(1 downto 0);
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o_sdr_n_CAS : out std_logic_vector(1 downto 0);
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o_sdr_n_WE : out std_logic_vector(1 downto 0);
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o_sdr_BA : out std_logic_vector(3 downto 0);
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o_sdr_ADDR : out std_logic_vector(25 downto 0);
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o_sdr_DATA : out std_logic_vector(31 downto 0);
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o_sdr_DATA_oe : out std_logic_vector(31 downto 0);
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i_sdr_DATA : in std_logic_vector(31 downto 0);
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o_sdr_DQM : out std_logic_vector(3 downto 0));
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END COMPONENT;
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---------------------- End COMPONENT Declaration ------------
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------------- Begin Cut here for INSTANTIATION Template -----
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u_sdram_controller : sdram_controller
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PORT MAP (
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i_aresetn => i_aresetn,
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i_AXI4_AWADDR => i_AXI4_AWADDR,
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i_sysclk => i_sysclk,
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i_sdrclk => i_sdrclk,
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i_tACclk => i_tACclk,
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i_pll_locked => i_pll_locked,
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o_dbg_ref_req => o_dbg_ref_req,
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o_dbg_wr_ack => o_dbg_wr_ack,
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o_dbg_rd_ack => o_dbg_rd_ack,
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o_dbg_n_CS => o_dbg_n_CS,
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o_dbg_n_RAS => o_dbg_n_RAS,
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o_dbg_n_CAS => o_dbg_n_CAS,
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o_dbg_n_WE => o_dbg_n_WE,
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o_dbg_BA => o_dbg_BA,
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o_dbg_ADDR => o_dbg_ADDR,
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o_dbg_DATA_out => o_dbg_DATA_out,
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o_dbg_DATA_in => o_dbg_DATA_in,
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o_pll_reset => o_pll_reset,
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o_AXI4_AWREADY => o_AXI4_AWREADY,
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i_AXI4_AWVALID => i_AXI4_AWVALID,
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o_AXI4_WREADY => o_AXI4_WREADY,
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i_AXI4_WDATA => i_AXI4_WDATA,
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i_AXI4_WSTRB => i_AXI4_WSTRB,
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i_AXI4_WLAST => i_AXI4_WLAST,
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i_AXI4_WVALID => i_AXI4_WVALID,
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o_AXI4_BVALID => o_AXI4_BVALID,
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i_AXI4_BREADY => i_AXI4_BREADY,
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o_AXI4_ARREADY => o_AXI4_ARREADY,
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i_AXI4_ARADDR => i_AXI4_ARADDR,
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i_AXI4_RREADY => i_AXI4_RREADY,
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o_AXI4_RDATA => o_AXI4_RDATA,
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o_AXI4_RLAST => o_AXI4_RLAST,
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o_AXI4_RVALID => o_AXI4_RVALID,
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i_AXI4_AWID => i_AXI4_AWID,
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i_AXI4_AWSIZE => i_AXI4_AWSIZE,
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i_AXI4_ARVALID => i_AXI4_ARVALID,
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i_AXI4_ARID => i_AXI4_ARID,
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i_AXI4_ARLEN => i_AXI4_ARLEN,
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i_AXI4_ARSIZE => i_AXI4_ARSIZE,
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i_AXI4_ARBURST => i_AXI4_ARBURST,
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i_AXI4_AWLEN => i_AXI4_AWLEN,
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o_AXI4_RID => o_AXI4_RID,
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o_dbg_we => o_dbg_we,
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o_dbg_last => o_dbg_last,
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o_dbg_addr => o_dbg_addr,
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o_dbg_din => o_dbg_din,
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o_axi4_wrstate => o_axi4_wrstate,
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o_fifo_wr => o_fifo_wr,
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o_fifo_full => o_fifo_full,
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o_fifo_empty => o_fifo_empty,
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o_dbg_fifo_waddr => o_dbg_fifo_waddr,
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o_dbg_fifo_re => o_dbg_fifo_re,
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o_dbg_fifo_raddr => o_dbg_fifo_raddr,
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o_dbg_fifo_we => o_dbg_fifo_we,
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o_dbg_axi4_wlast => o_dbg_axi4_wlast,
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o_shift_cnt => o_shift_cnt,
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o_re_lock => o_re_lock,
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o_axi4_rastate => o_axi4_rastate,
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o_axi4_nwr => o_axi4_nwr,
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o_axi4_arlen => o_axi4_arlen,
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o_axi4_rdstate => o_axi4_rdstate,
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o_sdr_rd_valid => o_sdr_rd_valid,
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o_sdr_dout => o_sdr_dout,
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o_dbg_re => o_dbg_re,
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o_AXI4_BID => o_AXI4_BID,
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i_addr => i_addr,
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i_din => i_din,
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i_dm => i_dm,
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o_dout => o_dout,
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o_sdr_state => o_sdr_state,
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o_sdr_init_done => o_sdr_init_done,
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o_wr_ack => o_wr_ack,
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o_rd_ack => o_rd_ack,
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o_ref_req => o_ref_req,
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o_rd_valid => o_rd_valid,
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o_sdr_CKE => o_sdr_CKE,
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o_sdr_n_CS => o_sdr_n_CS,
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o_sdr_n_RAS => o_sdr_n_RAS,
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o_sdr_n_CAS => o_sdr_n_CAS,
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o_sdr_n_WE => o_sdr_n_WE,
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o_sdr_BA => o_sdr_BA,
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o_sdr_ADDR => o_sdr_ADDR,
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o_sdr_DATA => o_sdr_DATA,
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o_sdr_DATA_oe => o_sdr_DATA_oe,
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i_sdr_DATA => i_sdr_DATA,
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o_sdr_DQM => o_sdr_DQM);
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------------------------ End INSTANTIATION Template ---------
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