44 lines
1.3 KiB
JSON
44 lines
1.3 KiB
JSON
{
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"args": [
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"-o",
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"sdram_controller",
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"--base_path",
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"/home/byron/Projects/super6502/hw/efinix_fpga/ip",
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"--vlnv",
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{
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"vendor": "efinixinc.com",
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"library": "memory_controller",
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"name": "efx_sdram_controller",
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"version": "1.6"
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}
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],
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"conf": {
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"fCK_MHz": "200",
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"tIORT_u": "2",
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"CL": "3",
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"DDIO_TYPE": "0",
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"DQ_GROUP": "2",
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"ROW_WIDTH": "13",
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"COL_WIDTH": "9",
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"tPWRUP": "200000",
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"tRAS": "44",
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"tRAS_MAX": "120000",
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"tRC": "66",
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"tRCD": "20",
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"tREF": "64000000",
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"tRFC ": "66",
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"tRP": "20",
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"SDRAM_MODE": "0",
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"DATA_RATE": "2"
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},
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"output": {
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"external_source": [
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"/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller.v",
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"/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.v",
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"/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller_define.vh",
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"/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.vhd"
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]
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},
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"sw_version": "2022.1.226",
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"generated_date": "2022-12-22T03:56:49.168890"
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} |