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bslathi19
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super6502
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d3ea5ed4d1ada8842481937d00426e7fcd22034c
super6502
/
hw
/
efinix_fpga
/
simulation
/
src
History
Byron Lathi
8e70e5a7c4
Update verilog sd
2023-10-10 21:40:24 -07:00
..
sim_uart
Add sim uart
2023-09-27 22:15:27 -07:00
verilog-6502
@
aaf4c084ef
Update verilog-6502
bslathi19/verilog-6502@aaf4c084ef
2023-09-26 23:15:22 -07:00
verilog-sd-emulator
@
390b7221db
Update verilog sd
2023-10-10 21:40:24 -07:00
generic_sdr.v
Disable sdr debug, initialize uart status
2023-09-27 21:14:09 -07:00
sim_top.sv
Increase sim time, update verilog sd
2023-10-10 21:39:10 -07:00