Files
super6502/.gitlab-ci.yml
2022-03-05 22:39:36 -06:00

26 lines
421 B
YAML

default:
tags:
- docker
build-sw:
stage: build
image: a2geek/cc65-pipeline
script:
- cd sw/
- make
build-fpga:
stage: build
image: bslathi19/modelsim_18.1:lite
script:
- cd hw/fpga/
- quartus_map super6502 -c super6502
test_addr_decode:
stage: test
image: bslathi19/modelsim_18.1:lite
script:
- cd hw/fpga/simulation/modelsim/
- vsim -do "do cs_testbench.do"