70 lines
1.4 KiB
Systemverilog
70 lines
1.4 KiB
Systemverilog
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module super6502(
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input clk,
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input logic rst,
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input logic [15:0] cpu_addr,
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inout logic [7:0] cpu_data,
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input logic cpu_vpb,
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input logic cpu_mlb,
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input logic cpu_rwb,
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input logic cpu_sync,
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output logic cpu_led,
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output logic cpu_resb,
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output logic cpu_rdy,
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output logic cpu_sob,
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output logic cpu_irqb,
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output logic cpu_phi2,
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output logic cpu_be,
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output logic cpu_nmib
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);
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logic [7:0] cpu_data_in;
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assign cpu_data_in = cpu_data;
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logic [7:0] cpu_data_out;
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assign cpu_data = cpu_rwb ? cpu_data_out : 'z;
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logic [2:0] clk_count;
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always_ff @(posedge clk) begin
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clk_count <= clk_count + 3'b1;
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if (clk_count == 3'h4) begin
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clk_count <= '0;
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cpu_phi2 <= ~cpu_phi2;
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end
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end
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always_comb begin
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if (ram_cs)
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cpu_data_out = ram_data_out;
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else
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cpu_data_out = rom_data_out;
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end
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logic [7:0] ram_data_out;
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logic ram_cs;
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assign ram_cs = ~cpu_addr[15];
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ram main_memory(
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.address(cpu_addr[14:0]),
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.clock(clk),
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.data(cpu_data_in),
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.wren(~cpu_rwb & ram_cs),
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.q(ram_data_out)
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);
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logic [7:0] rom_data_out;
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rom boot_rom(
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.address(cpu_addr[14:0]),
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.clock(clk),
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.q(rom_data_out)
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);
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endmodule
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