103 lines
1.7 KiB
Systemverilog
103 lines
1.7 KiB
Systemverilog
module sim();
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timeunit 10ns;
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timeprecision 1ns;
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logic clk_50;
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logic i_clk;
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logic i_rst;
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logic i_cs;
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logic i_rwb;
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logic [1:0] i_addr;
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logic [7:0] i_data;
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logic [7:0] o_data;
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logic o_spi_cs;
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logic o_spi_clk;
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logic o_spi_mosi;
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logic i_spi_miso;
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spi_controller dut(.*);
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always #1 clk_50 = clk_50 === 1'b0;
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always #100 i_clk = i_clk === 1'b0;
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task write_reg(input logic [2:0] _addr, input logic [7:0] _data);
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@(negedge i_clk);
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i_cs <= '1;
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i_addr <= _addr;
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i_rwb <= '0;
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i_data <= '1;
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@(posedge i_clk);
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i_data <= _data;
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@(negedge i_clk);
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i_cs <= '0;
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i_rwb <= '1;
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endtask
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task read_reg(input logic [2:0] _addr, output logic [7:0] _data);
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@(negedge i_clk);
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i_cs <= '1;
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i_addr <= _addr;
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i_rwb <= '1;
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i_data <= '1;
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@(posedge i_clk);
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_data <= o_data;
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@(negedge i_clk);
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i_cs <= '0;
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i_rwb <= '1;
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endtask
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initial
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begin
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$dumpfile("spi_controller.vcd");
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$dumpvars(0,sim);
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end
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logic [7:0] data;
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initial begin
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i_rst <= '1;
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repeat(5) @(posedge i_clk);
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i_cs <= '0;
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i_rwb <= '1;
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i_addr <= '0;
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i_rst <= '0;
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repeat(5) @(posedge i_clk);
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write_reg(3, 1);
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write_reg(2, 8'hFF);
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data = (1 << 7);
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while(data & (1 << 7)) begin
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read_reg(3, data);
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end
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write_reg(3, 0);
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read_reg(1, data);
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assert(data == 8'h55);
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repeat(50) @(posedge i_clk);
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$finish();
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end
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logic [7:0] _spi_device_data;
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initial begin
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_spi_device_data <= 8'h55;
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end
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always @(edge o_spi_clk) begin
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if (o_spi_cs == '0) begin
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if (o_spi_clk == '1)
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i_spi_miso <= _spi_device_data[7];
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if (o_spi_clk == '0)
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_spi_device_data <= _spi_device_data << 1;
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end
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end
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endmodule
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