76 lines
1.1 KiB
Systemverilog
76 lines
1.1 KiB
Systemverilog
module sim();
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timeunit 10ns;
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timeprecision 1ns;
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logic clk;
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logic rwb;
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logic clk_50;
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logic reset;
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logic [2:0] addr;
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logic [7:0] i_data;
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logic [7:0] o_data;
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logic cs;
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logic irq;
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timer dut(
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.*);
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always #1 clk_50 = clk_50 === 1'b0;
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always #100 clk = clk === 1'b0;
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task write_reg(input logic [2:0] _addr, input logic [7:0] _data);
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@(negedge clk);
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cs <= '1;
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addr <= _addr;
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rwb <= '0;
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i_data <= '1;
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@(posedge clk);
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i_data <= _data;
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@(negedge clk);
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cs <= '0;
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rwb <= '1;
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endtask
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task read_reg(input logic [2:0] _addr, output logic [7:0] _data);
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@(negedge clk);
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cs <= '1;
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addr <= _addr;
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rwb <= '1;
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i_data <= '1;
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@(posedge clk);
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_data <= o_data;
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@(negedge clk);
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cs <= '0;
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rwb <= '1;
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endtask
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initial
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begin
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$dumpfile("timer.vcd");
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$dumpvars(0,sim);
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end
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logic [7:0] read_data;
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initial begin
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reset <= '1;
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repeat(5) @(posedge clk);
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reset <= '0;
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write_reg(5, 16);
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repeat(1024) @(posedge clk);
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repeat(10) begin
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read_reg(0, read_data);
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$display("Read: %d", read_data);
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repeat(1024) @(posedge clk);
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end
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$finish();
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end
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endmodule
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