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bslathi19
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super6502
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e7e1eab4a4ce63e442dedae8193ed4bc942de716
super6502
/
hw
/
efinix_fpga
/
simulation
/
src
History
Byron Lathi
e7e1eab4a4
Try long test
2023-10-23 18:54:51 -07:00
..
sim_uart
Add sim uart
2023-09-27 22:15:27 -07:00
verilog-6502
@
aaf4c084ef
Update verilog-6502
bslathi19/verilog-6502@aaf4c084ef
2023-09-26 23:15:22 -07:00
verilog-sd-emulator
@
72a7868fa9
Update to use new binary sd card image
2023-10-22 16:45:41 -07:00
generic_sdr.v
Disable sdr debug, initialize uart status
2023-09-27 21:14:09 -07:00
sim_top.sv
Try long test
2023-10-23 18:54:51 -07:00