62 lines
1.3 KiB
YAML
62 lines
1.3 KiB
YAML
default:
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tags:
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- docker
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build-kernel:
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stage: build
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image: a2geek/cc65-pipeline
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script:
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- cd sw/kernel
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- make
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build-fpga:
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stage: build
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image: bslathi19/modelsim_18.1:lite
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script:
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- cd hw/fpga/
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- qsys-generate /builds/bslathi19/super6502/hw/fpga/sdram_platform.qsys --synthesis=VERILOG --output-directory=/builds/bslathi19/super6502/hw/fpga/sdram_platform --family="MAX 10" --part=10M50DAF484C7G
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- quartus_map super6502 -c super6502
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test_addr_decode:
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stage: test
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image: bslathi19/modelsim_18.1:lite
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script:
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- cd hw/fpga/simulation/modelsim/
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- vsim -do "do cs_testbench.do"
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test_bb_spi:
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stage: test
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image: bslathi19/modelsim_18.1:lite
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script:
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- cd hw/fpga/simulation/modelsim/
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- vsim -do "do bb_spi_testbench.do"
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test-sw:
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stage: test
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image: a2geek/cc65-pipeline
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script:
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- cd sw/kernel
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- make test
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test_mm:
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stage: test
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image: bslathi19/modelsim_18.1:lite
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script:
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- cd hw/fpga/simulation/modelsim/
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- vsim -do "do mm_testbench.do"
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test_crc7:
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stage: test
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image: bslathi19/modelsim_18.1:lite
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script:
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- cd hw/fpga/simulation/modelsim/
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- vsim -do "do crc7_testbench.do"
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test_sd_cmd:
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stage: test
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image: bslathi19/modelsim_18.1:lite
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script:
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- cd hw/fpga/simulation/modelsim/
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- vsim -do "sd_cmd_testbench.do"
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