e70fffb472
Upon receiving an interrupt, the corresponding bit in the interrupt status register will be set and an IRQ will be raised for the CPU. The cpu can then respond to the interrupt and clear the interrupt by writing back to the interrupt status register.
144 lines
2.7 KiB
Systemverilog
144 lines
2.7 KiB
Systemverilog
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module super6502(
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input clk_50,
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input logic rst_n,
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input logic button_1,
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input logic [15:0] cpu_addr,
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inout logic [7:0] cpu_data,
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input logic cpu_vpb,
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input logic cpu_mlb,
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input logic cpu_rwb,
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input logic cpu_sync,
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output logic cpu_led,
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output logic cpu_resb,
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output logic cpu_rdy,
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output logic cpu_sob,
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output logic cpu_irqb,
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output logic cpu_phi2,
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output logic cpu_be,
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output logic cpu_nmib,
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output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5,
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input logic UART_RXD,
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output logic UART_TXD
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);
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logic rst;
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assign rst = ~rst_n;
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logic clk;
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logic [7:0] cpu_data_in;
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assign cpu_data_in = cpu_data;
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logic [7:0] cpu_data_out;
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assign cpu_data = cpu_rwb ? cpu_data_out : 'z;
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logic [7:0] rom_data_out;
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logic [7:0] ram_data_out;
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logic [7:0] uart_data_out;
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logic [7:0] irq_data_out;
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logic ram_cs;
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logic rom_cs;
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logic hex_cs;
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logic uart_cs;
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logic irq_cs;
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cpu_clk cpu_clk(
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.inclk0(clk_50),
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.c0(clk)
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);
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always @(posedge clk) begin
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cpu_phi2 <= ~cpu_phi2;
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end
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assign cpu_rdy = '1;
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assign cpu_sob = '0;
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assign cpu_resb = rst_n;
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assign cpu_be = '1;
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assign cpu_nmib = '1;
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assign cpu_irqb = irq_data_out == 0;
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addr_decode decode(
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.addr(cpu_addr),
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.ram_cs(ram_cs),
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.rom_cs(rom_cs),
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.hex_cs(hex_cs),
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.uart_cs(uart_cs),
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.irq_cs(irq_cs)
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);
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always_comb begin
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if (ram_cs)
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cpu_data_out = ram_data_out;
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else if (rom_cs)
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cpu_data_out = rom_data_out;
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else if (uart_cs)
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cpu_data_out = uart_data_out;
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else if (irq_cs)
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cpu_data_out = irq_data_out;
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else
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cpu_data_out = 'x;
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end
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ram main_memory(
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.address(cpu_addr[14:0]),
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.clock(clk),
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.data(cpu_data_in),
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.wren(~cpu_rwb & ram_cs),
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.q(ram_data_out)
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);
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rom boot_rom(
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.address(cpu_addr[14:0]),
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.clock(clk),
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.q(rom_data_out)
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);
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SevenSeg segs(
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.clk(clk),
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.rst(rst),
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.rw(cpu_rwb),
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.data(cpu_data_in),
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.cs(hex_cs),
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.addr(cpu_addr[1:0]),
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.HEX0(HEX0), .HEX1(HEX1), .HEX2(HEX2), .HEX3(HEX3), .HEX4(HEX4), .HEX5(HEX5)
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);
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uart uart(
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.clk_50(clk_50),
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.clk(clk),
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.rst(rst),
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.rw(cpu_rwb),
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.data_in(cpu_data_in),
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.cs(uart_cs),
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.addr(cpu_addr[1:0]),
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.RXD(UART_RXD),
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.TXD(UART_TXD),
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.data_out(uart_data_out)
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);
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always_ff @(posedge clk_50) begin
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if (rst)
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irq_data_out <= '0;
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else if (irq_cs && ~cpu_rwb)
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irq_data_out <= irq_data_out & cpu_data_in;
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else if (~button_1)
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irq_data_out <= {irq_data_out[7:1], ~button_1};
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end
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endmodule
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