f8da9206d9
Added new signal tx_flag, which indicates whether the transmitter is ready for new data. Added status register, which when read will return the tx_flag bit, as well as others that can be implemented. Added new state IDLE, which resets the TX flag and allows new data to be written. Added code to allow for different baud rates, though it is still fixed currently.
152 lines
2.9 KiB
Systemverilog
152 lines
2.9 KiB
Systemverilog
module uart(
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input clk_50,
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input clk,
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input rst,
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input cs,
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input rw,
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input [7:0] data_in,
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input [1:0] addr,
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input RXD,
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output logic TXD,
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output logic [7:0] data_out
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);
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//Handle reading and writing registers
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logic [7:0] tx_buf;
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logic [7:0] rx_buf;
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logic [7:0] status;
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logic tx_flag;
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logic tx_flag_set;
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logic tx_flag_clear;
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assign status[0] = tx_flag | tx_flag_clear;
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always_ff @(posedge clk) begin
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if (rst) begin
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tx_flag_set <= '0;
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tx_buf <= '0;
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rx_buf <= '0;
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status[7:1] <= '0;
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end
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if (cs) begin
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if (~rw) begin
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if (addr == 0)
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tx_buf <= data_in;
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end else begin
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if (addr == 0)
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data_out <= rx_buf;
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if (addr == 1)
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data_out <= status;
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end
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end
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if (~rw & cs && addr == 0)
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tx_flag_set <= '1;
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else
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tx_flag_set <= '0;
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end
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// state controller
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typedef enum bit [2:0] {START, DATA, PARITY, STOP, IDLE} macro_t;
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struct packed {
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macro_t macro;
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logic [3:0] count;
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} state, next_state;
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localparam logic [3:0] maxcount = 4'h7;
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// baud rate: 9600
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localparam baud = 9600;
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localparam count = (50000000/baud)-1;
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logic [14:0] clkdiv;
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always_ff @(posedge clk_50) begin
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if (rst) begin
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clkdiv <= 0;
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state.macro <= IDLE;
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state.count <= 3'b0;
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tx_flag <= '0;
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end else begin
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if (tx_flag_set)
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tx_flag <= '1;
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else if (tx_flag_clear)
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tx_flag <= '0;
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if (clkdiv == count) begin
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clkdiv <= 0;
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state <= next_state;
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end else begin
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clkdiv <= clkdiv + 15'b1;
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end
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end
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end
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always_comb begin
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next_state = state;
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unique case (state.macro)
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START: begin
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next_state.macro = DATA;
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next_state.count = 3'b0;
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end
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DATA: begin
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if (state.count == maxcount) begin
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next_state.macro = STOP; // or PARITY
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next_state.count = 3'b0;
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end else begin
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next_state.count = state.count + 3'b1;
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next_state.macro = DATA;
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end
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end
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PARITY: begin
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end
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STOP: begin
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next_state.macro = IDLE;
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next_state.count = '0;
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end
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IDLE: begin
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if (tx_flag)
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next_state.macro = START;
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else
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next_state.macro = IDLE;
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end
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default:;
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endcase
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end
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always_comb begin
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TXD = '1;
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tx_flag_clear = '0;
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unique case (state.macro)
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START: begin
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TXD = '0;
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end
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DATA: begin
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TXD = tx_buf[state.count];
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end
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PARITY: begin
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end
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STOP: begin
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tx_flag_clear = '1;
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TXD = '1;
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end
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IDLE: begin
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TXD = '1;
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end
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default:;
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endcase
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end
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endmodule
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