9 lines
392 B
Plaintext
9 lines
392 B
Plaintext
hvl/sim_top.sv
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sub/verilog-6502/ALU.v
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sub/verilog-6502/cpu_65c02.v
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sub/sim_sdram/generic_sdr.v
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../sub/sd_controller_wrapper/sdspi/bench/verilog/mdl_sdio.v
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../sub/sd_controller_wrapper/sdspi/bench/verilog/mdl_sdcmd.v
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../sub/sd_controller_wrapper/sdspi/bench/verilog/mdl_sdrx.v
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../sub/sd_controller_wrapper/sdspi/bench/verilog/mdl_sdtx.v
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../sub/sd_controller_wrapper/sdspi/bench/verilog/IOBUF.v |