fcae23785e
I think that previously, I had not actually commited any of this to git. This adds all of the new effinix stuff that I had been working on for months. The gist of all of this is that the intel fpga is expensive and does not exist, whereas the effinix ones are not as expensive and more existant. This redoes the project to use the dev board, as well as a custom board that I may or may not make.
107 lines
2.2 KiB
Systemverilog
107 lines
2.2 KiB
Systemverilog
module crc7 #(parameter POLYNOMIAL = 8'h89)
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(
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input clk,
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input rst,
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input load,
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input [39:0] data_in,
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output logic [6:0] crc_out,
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output logic valid
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);
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logic [46:0] data;
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logic [46:0] next_data;
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logic [46:0] polyshift;
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typedef enum bit [1:0] {IDLE, WORKING, VALID} macro_t;
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struct packed {
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macro_t macro;
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logic [5:0] count;
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} state, next_state;
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always_ff @(posedge clk) begin
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if (rst) begin
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polyshift <= {POLYNOMIAL, 39'b0}; //start all the way at the left
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data <= '0;
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state.macro <= IDLE;
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state.count <= '0;
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end else begin
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if (load) begin
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data <= {data_in, 7'b0};
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end else begin
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data <= next_data;
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end
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state <= next_state;
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if (state.macro == WORKING) begin
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polyshift <= polyshift >> 1;
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end
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if (state.macro == VALID) begin
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polyshift <= {POLYNOMIAL, 39'b0};
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end
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end
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end
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always_comb begin
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next_state = state;
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case (state.macro)
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IDLE: begin
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if (load) begin
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next_state.macro = WORKING;
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next_state.count = '0;
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end
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end
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WORKING: begin
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if (state.count < 39) begin
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next_state.count = state.count + 6'b1;
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end else begin
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next_state.macro = VALID;
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next_state.count = '0;
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end
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end
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VALID: begin // Same as IDLE, but IDLE is just for reset.
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if (load) begin
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next_state.macro = WORKING;
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next_state.count = '0;
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end
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end
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default:;
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endcase
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end
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always_comb begin
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valid = 0;
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next_data = '0;
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crc_out = '0;
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case (state.macro)
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IDLE: begin
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valid = 0;
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end
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WORKING: begin
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if (data[6'd46 - state.count]) begin
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next_data = data ^ polyshift;
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end else begin
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next_data = data;
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end
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end
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VALID: begin
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valid = ~load;
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next_data = data;
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crc_out = data[6:0];
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end
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default:;
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endcase
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end
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endmodule
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