fcae23785e
I think that previously, I had not actually commited any of this to git. This adds all of the new effinix stuff that I had been working on for months. The gist of all of this is that the intel fpga is expensive and does not exist, whereas the effinix ones are not as expensive and more existant. This redoes the project to use the dev board, as well as a custom board that I may or may not make.
84 lines
3.8 KiB
Verilog
84 lines
3.8 KiB
Verilog
////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
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//
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// This document contains proprietary information which is
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// protected by copyright. All rights are reserved. This notice
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// refers to original work by Efinix, Inc. which may be derivitive
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// of other work distributed under license of the authors. In the
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// case of derivative work, nothing in this notice overrides the
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// original author's license agreement. Where applicable, the
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// original license agreement is included in it's original
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// unmodified form immediately below this header.
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//
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// WARRANTY DISCLAIMER.
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// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
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// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
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// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
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// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
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// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
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// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
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// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
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//
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// LIMITATION OF LIABILITY.
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// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
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// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
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// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
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// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
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// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
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// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
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// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
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// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
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// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
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// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
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// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
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// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
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// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
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// APPLY TO LICENSEE.
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//
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////////////////////////////////////////////////////////////////////////////////
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sdram u_sdram(
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.i_we ( i_we ),
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.i_sysclk ( i_sysclk ),
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.i_arst ( i_arst ),
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.i_sdrclk ( i_sdrclk ),
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.i_tACclk ( i_tACclk ),
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.i_pll_locked ( i_pll_locked ),
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.i_re ( i_re ),
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.i_last ( i_last ),
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.o_dbg_tRTW_done ( o_dbg_tRTW_done ),
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.o_dbg_ref_req ( o_dbg_ref_req ),
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.o_dbg_wr_ack ( o_dbg_wr_ack ),
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.o_dbg_rd_ack ( o_dbg_rd_ack ),
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.o_dbg_n_CS ( o_dbg_n_CS ),
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.o_dbg_n_RAS ( o_dbg_n_RAS ),
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.o_dbg_n_CAS ( o_dbg_n_CAS ),
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.o_dbg_n_WE ( o_dbg_n_WE ),
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.o_dbg_BA ( o_dbg_BA ),
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.o_dbg_ADDR ( o_dbg_ADDR ),
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.o_dbg_DATA_out ( o_dbg_DATA_out ),
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.o_dbg_DATA_in ( o_dbg_DATA_in ),
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.i_addr ( i_addr ),
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.i_din ( i_din ),
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.o_dout ( o_dout ),
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.o_sdr_state ( o_sdr_state ),
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.o_sdr_init_done ( o_sdr_init_done ),
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.o_wr_ack ( o_wr_ack ),
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.o_rd_ack ( o_rd_ack ),
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.o_ref_req ( o_ref_req ),
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.o_rd_valid ( o_rd_valid ),
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.o_sdr_CKE ( o_sdr_CKE ),
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.o_sdr_n_CS ( o_sdr_n_CS ),
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.o_sdr_n_RAS ( o_sdr_n_RAS ),
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.o_sdr_n_CAS ( o_sdr_n_CAS ),
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.o_sdr_n_WE ( o_sdr_n_WE ),
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.o_sdr_BA ( o_sdr_BA ),
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.o_sdr_ADDR ( o_sdr_ADDR ),
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.o_sdr_DATA ( o_sdr_DATA ),
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.o_sdr_DATA_oe ( o_sdr_DATA_oe ),
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.i_sdr_DATA ( i_sdr_DATA ),
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.o_sdr_DQM ( o_sdr_DQM ),
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.o_dbg_dly_cnt_b ( o_dbg_dly_cnt_b ),
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.o_dbg_tRCD_done ( o_dbg_tRCD_done )
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);
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