fcae23785e
I think that previously, I had not actually commited any of this to git. This adds all of the new effinix stuff that I had been working on for months. The gist of all of this is that the intel fpga is expensive and does not exist, whereas the effinix ones are not as expensive and more existant. This redoes the project to use the dev board, as well as a custom board that I may or may not make.
84 lines
5.4 KiB
XML
84 lines
5.4 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<efx:project name="super6502" description="" last_change_date="Wed August 17 2022 12:17:48" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2021.2.323.4.6" last_run_state="fail" last_run_tool="efx_map" last_run_flow="syn" config_result_in_sync="true" design_ood="" place_ood="" route_ood="" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
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<efx:device_info>
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<efx:family name="Trion"/>
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<efx:device name="T20F256"/>
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<efx:timing_model name="C3"/>
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</efx:device_info>
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<efx:design_info def_veri_version="sv_09" def_vhdl_version="vhdl_2008">
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<efx:top_module name="super6502"/>
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<efx:design_file name="super6502.sv" version="default" library="default"/>
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<efx:design_file name="crc7.sv" version="default" library="default"/>
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<efx:design_file name="memory_mapper.sv" version="default" library="default"/>
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<efx:design_file name="uart.sv" version="default" library="default"/>
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<efx:design_file name="HexDriver.sv" version="default" library="default"/>
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<efx:design_file name="addr_decode.sv" version="default" library="default"/>
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<efx:design_file name="board_io.sv" version="default" library="default"/>
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<efx:design_file name="SevenSeg.sv" version="default" library="default"/>
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<efx:design_file name="sd_controller.sv" version="default" library="default"/>
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<efx:design_file name="sdram_adapter.sv" version="default" library="default"/>
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<efx:top_vhdl_arch name=""/>
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</efx:design_info>
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<efx:constraint_info>
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<efx:sdc_file name=""/>
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<efx:inter_file name=""/>
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</efx:constraint_info>
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<efx:sim_info/>
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<efx:misc_info/>
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<efx:ip_info>
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<efx:ip instance_name="sdram" path="ip/sdram/settings.json">
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<efx:ip_src_file name="sdram.v"/>
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</efx:ip>
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</efx:ip_info>
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<efx:synthesis tool_name="efx_map">
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<efx:param name="work_dir" value="work_syn" value_type="e_string"/>
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<efx:param name="write_efx_verilog" value="on" value_type="e_bool"/>
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<efx:param name="mode" value="speed" value_type="e_option"/>
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<efx:param name="max_ram" value="-1" value_type="e_integer"/>
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<efx:param name="max_mult" value="-1" value_type="e_integer"/>
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<efx:param name="infer-clk-enable" value="3" value_type="e_option"/>
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<efx:param name="infer-sync-set-reset" value="1" value_type="e_option"/>
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<efx:param name="fanout-limit" value="0" value_type="e_integer"/>
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<efx:param name="bram_output_regs_packing" value="1" value_type="e_option"/>
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<efx:param name="retiming" value="1" value_type="e_option"/>
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<efx:param name="seq_opt" value="1" value_type="e_option"/>
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<efx:param name="blast_const_operand_adders" value="1" value_type="e_option"/>
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<efx:param name="operator-sharing" value="0" value_type="e_option"/>
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<efx:param name="optimize-adder-tree" value="0" value_type="e_option"/>
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<efx:param name="mult_input_regs_packing" value="1" value_type="e_option"/>
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<efx:param name="mult_output_regs_packing" value="1" value_type="e_option"/>
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<efx:param name="include" value="ip/sdram" value_type="e_string"/>
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</efx:synthesis>
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<efx:place_and_route tool_name="efx_pnr">
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<efx:param name="work_dir" value="work_pnr" value_type="e_string"/>
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<efx:param name="verbose" value="off" value_type="e_bool"/>
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<efx:param name="load_delaym" value="on" value_type="e_bool"/>
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<efx:param name="optimization_level" value="NULL" value_type="e_option"/>
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<efx:param name="seed" value="1" value_type="e_integer"/>
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</efx:place_and_route>
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<efx:bitstream_generation tool_name="efx_pgm">
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<efx:param name="mode" value="active" value_type="e_string"/>
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<efx:param name="width" value="1" value_type="e_string"/>
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<efx:param name="enable_roms" value="smart" value_type="e_option"/>
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<efx:param name="spi_low_power_mode" value="on" value_type="e_bool"/>
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<efx:param name="io_weak_pullup" value="on" value_type="e_bool"/>
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<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option"/>
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<efx:param name="bitstream_compression" value="on" value_type="e_bool"/>
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<efx:param name="enable_external_master_clock" value="off" value_type="e_bool"/>
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<efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option"/>
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<efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string"/>
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<efx:param name="release_tri_then_reset" value="on" value_type="e_bool"/>
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<efx:param name="cold_boot" value="off" value_type="e_bool"/>
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<efx:param name="cascade" value="off" value_type="e_option"/>
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<efx:param name="generate_bit" value="on" value_type="e_bool"/>
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<efx:param name="generate_bitbin" value="off" value_type="e_bool"/>
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<efx:param name="generate_hex" value="on" value_type="e_bool"/>
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<efx:param name="generate_hexbin" value="off" value_type="e_bool"/>
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</efx:bitstream_generation>
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<efx:debugger>
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<efx:param name="work_dir" value="work_dbg" value_type="e_string"/>
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<efx:param name="auto_instantiation" value="off" value_type="e_bool"/>
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<efx:param name="profile" value="NONE" value_type="e_string"/>
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</efx:debugger>
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</efx:project>
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