diff --git a/README.md b/README.md index 6f0d321..6730b10 100644 --- a/README.md +++ b/README.md @@ -40,6 +40,7 @@ To facilitate the dual-license model, contributions to the project can only be a * SV interface for AXI lite * AXI lite to AXI adapter * AXI lite to APB adapter + * Crossbar * Interconnect * Register slice * Width converter diff --git a/src/axi/rtl/taxi_axil_crossbar.f b/src/axi/rtl/taxi_axil_crossbar.f new file mode 100644 index 0000000..0717497 --- /dev/null +++ b/src/axi/rtl/taxi_axil_crossbar.f @@ -0,0 +1,3 @@ +taxi_axil_crossbar.sv +taxi_axil_crossbar_wr.f +taxi_axil_crossbar_rd.f diff --git a/src/axi/rtl/taxi_axil_crossbar.sv b/src/axi/rtl/taxi_axil_crossbar.sv new file mode 100644 index 0000000..12331b6 --- /dev/null +++ b/src/axi/rtl/taxi_axil_crossbar.sv @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2021-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 lite crossbar + */ +module taxi_axil_crossbar # +( + // Number of AXI inputs (slave interfaces) + parameter S_COUNT = 4, + // Number of AXI outputs (master interfaces) + parameter M_COUNT = 4, + // Address width in bits for address decoding + parameter ADDR_W = 32, + // TODO fix parametrization once verilator issue 5890 is fixed + // Number of concurrent operations for each slave interface + // S_COUNT concatenated fields of 32 bits + parameter S_ACCEPT = {S_COUNT{32'd16}}, + // Number of regions per master interface + parameter M_REGIONS = 1, + // Master interface base addresses + // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits + // set to zero for default addressing based on M_ADDR_W + parameter M_BASE_ADDR = '0, + // Master interface address widths + // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits + parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}}, + // Read connections between interfaces + // M_COUNT concatenated fields of S_COUNT bits + parameter M_CONNECT_RD = {M_COUNT{{S_COUNT{1'b1}}}}, + // Write connections between interfaces + // M_COUNT concatenated fields of S_COUNT bits + parameter M_CONNECT_WR = {M_COUNT{{S_COUNT{1'b1}}}}, + // Number of concurrent operations for each master interface + // M_COUNT concatenated fields of 32 bits + parameter M_ISSUE = {M_COUNT{32'd16}}, + // Secure master (fail operations based on awprot/arprot) + // M_COUNT bits + parameter M_SECURE = {M_COUNT{1'b0}}, + // Slave interface AW channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S_AW_REG_TYPE = {S_COUNT{2'd0}}, + // Slave interface W channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S_W_REG_TYPE = {S_COUNT{2'd0}}, + // Slave interface B channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S_B_REG_TYPE = {S_COUNT{2'd1}}, + // Slave interface AR channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S_AR_REG_TYPE = {S_COUNT{2'd0}}, + // Slave interface R channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S_R_REG_TYPE = {S_COUNT{2'd2}}, + // Master interface AW channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M_AW_REG_TYPE = {M_COUNT{2'd1}}, + // Master interface W channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M_W_REG_TYPE = {M_COUNT{2'd2}}, + // Master interface B channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M_B_REG_TYPE = {M_COUNT{2'd0}}, + // Master interface AR channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M_AR_REG_TYPE = {M_COUNT{2'd1}}, + // Master interface R channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M_R_REG_TYPE = {M_COUNT{2'd0}} +) +( + input wire logic clk, + input wire logic rst, + + /* + * AXI4-lite slave interfaces + */ + taxi_axil_if.wr_slv s_axil_wr[S_COUNT], + taxi_axil_if.rd_slv s_axil_rd[S_COUNT], + + /* + * AXI4-lite master interfaces + */ + taxi_axil_if.wr_mst m_axil_wr[M_COUNT], + taxi_axil_if.rd_mst m_axil_rd[M_COUNT] +); + +taxi_axil_crossbar_wr #( + .S_COUNT(S_COUNT), + .M_COUNT(M_COUNT), + .ADDR_W(ADDR_W), + .S_ACCEPT(S_ACCEPT), + .M_REGIONS(M_REGIONS), + .M_BASE_ADDR(M_BASE_ADDR), + .M_ADDR_W(M_ADDR_W), + .M_CONNECT(M_CONNECT_WR), + .M_ISSUE(M_ISSUE), + .M_SECURE(M_SECURE), + .S_AW_REG_TYPE(S_AW_REG_TYPE), + .S_W_REG_TYPE(S_W_REG_TYPE), + .S_B_REG_TYPE(S_B_REG_TYPE) +) +wr_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI lite slave interfaces + */ + .s_axil_wr(s_axil_wr), + + /* + * AXI lite master interfaces + */ + .m_axil_wr(m_axil_wr) +); + +taxi_axil_crossbar_rd #( + .S_COUNT(S_COUNT), + .M_COUNT(M_COUNT), + .ADDR_W(ADDR_W), + .S_ACCEPT(S_ACCEPT), + .M_REGIONS(M_REGIONS), + .M_BASE_ADDR(M_BASE_ADDR), + .M_ADDR_W(M_ADDR_W), + .M_CONNECT(M_CONNECT_RD), + .M_ISSUE(M_ISSUE), + .M_SECURE(M_SECURE), + .S_AR_REG_TYPE(S_AR_REG_TYPE), + .S_R_REG_TYPE(S_R_REG_TYPE) +) +rd_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI lite slave interfaces + */ + .s_axil_rd(s_axil_rd), + + /* + * AXI lite master interfaces + */ + .m_axil_rd(m_axil_rd) +); + +endmodule + +`resetall diff --git a/src/axi/rtl/taxi_axil_crossbar_addr.sv b/src/axi/rtl/taxi_axil_crossbar_addr.sv new file mode 100644 index 0000000..b2fda3c --- /dev/null +++ b/src/axi/rtl/taxi_axil_crossbar_addr.sv @@ -0,0 +1,301 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2021-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 lite crossbar address decode and admission control + */ +module taxi_axil_crossbar_addr # +( + // Slave interface index + parameter S = 0, + // Number of AXI inputs (slave interfaces) + parameter S_COUNT = 4, + // Number of AXI outputs (master interfaces) + parameter M_COUNT = 4, + // Select signal width + parameter SEL_W = $clog2(M_COUNT), + // Address width in bits for address decoding + parameter ADDR_W = 32, + // Address width in bits for address decoding + parameter STRB_W = 4, + // TODO fix parametrization once verilator issue 5890 is fixed + // Number of regions per master interface + parameter M_REGIONS = 1, + // Master interface base addresses + // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits + // set to zero for default addressing based on M_ADDR_W + parameter M_BASE_ADDR = '0, + // Master interface address widths + // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits + parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}}, + // Connections between interfaces + // M_COUNT concatenated fields of S_COUNT bits + parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}}, + // Secure master (fail operations based on awprot/arprot) + // M_COUNT bits + parameter M_SECURE = {M_COUNT{1'b0}}, + // Enable write command output + parameter WC_OUTPUT = 0 +) +( + input wire logic clk, + input wire logic rst, + + /* + * Address input + */ + input wire logic [ADDR_W-1:0] s_axil_aaddr, + input wire logic [2:0] s_axil_aprot, + input wire logic s_axil_avalid, + output wire logic s_axil_aready, + + /* + * Select output + */ + output wire logic [SEL_W-1:0] m_select, + output wire logic m_axil_avalid, + input wire logic m_axil_aready, + + /* + * Write command output + */ + output wire logic [SEL_W-1:0] m_wc_select, + output wire logic m_wc_decerr, + output wire logic m_wc_valid, + input wire logic m_wc_ready, + + /* + * Reply command output + */ + output wire logic [SEL_W-1:0] m_rc_select, + output wire logic m_rc_decerr, + output wire logic m_rc_valid, + input wire logic m_rc_ready +); + +localparam CL_S_COUNT = $clog2(S_COUNT); +localparam CL_M_COUNT = $clog2(M_COUNT); +localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1; +localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1; + +localparam [M_COUNT*M_REGIONS-1:0][31:0] M_ADDR_W_INT = M_ADDR_W; +localparam [M_COUNT-1:0][S_COUNT-1:0] M_CONNECT_INT = M_CONNECT; +localparam [M_COUNT-1:0] M_SECURE_INT = M_SECURE; + +// default address computation +function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy); + logic [ADDR_W-1:0] base; + logic [ADDR_W-1:0] width; + logic [ADDR_W-1:0] size; + logic [ADDR_W-1:0] mask; + begin + calcBaseAddrs = '0; + base = 0; + for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin + width = M_ADDR_W_INT[i]; + mask = {ADDR_W{1'b1}} >> (ADDR_W - width); + size = mask + 1; + if (width > 0) begin + if ((base & mask) != 0) begin + base = base + size - (base & mask); // align + end + calcBaseAddrs[i] = base; + base = base + size; // increment + end + end + end +endfunction + +localparam [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] M_BASE_ADDR_INT = M_BASE_ADDR != 0 ? (M_COUNT*M_REGIONS*ADDR_W)'(M_BASE_ADDR) : calcBaseAddrs(0); + +// check configuration +if (M_REGIONS < 1) + $fatal(0, "Error: M_REGIONS must be at least 1 (instance %m)"); + +initial begin + for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin + /* verilator lint_off UNSIGNED */ + if (M_ADDR_W_INT[i] != 0 && (M_ADDR_W_INT[i] < $clog2(STRB_W) || M_ADDR_W_INT[i] > ADDR_W)) begin + $error("Error: address width out of range (instance %m)"); + $finish; + end + /* verilator lint_on UNSIGNED */ + end + + $display("Addressing configuration for axil_crossbar_addr instance %m"); + for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin + if (M_ADDR_W_INT[i] != 0) begin + $display("%2d (%2d): %x / %02d -- %x-%x", + i/M_REGIONS, i%M_REGIONS, + M_BASE_ADDR_INT[i], + M_ADDR_W_INT[i], + M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]), + M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i])) + ); + end + end + + for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin + if ((M_BASE_ADDR_INT[i] & (2**M_ADDR_W_INT[i]-1)) != 0) begin + $display("Region not aligned:"); + $display("%2d (%2d): %x / %2d -- %x-%x", + i/M_REGIONS, i%M_REGIONS, + M_BASE_ADDR_INT[i], + M_ADDR_W_INT[i], + M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]), + M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i])) + ); + $error("Error: address range not aligned (instance %m)"); + $finish; + end + end + + for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin + for (integer j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin + if (M_ADDR_W_INT[i] != 0 && M_ADDR_W_INT[j] != 0) begin + if (((M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i])) <= (M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j])))) + && ((M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j])) <= (M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))))) begin + $display("Overlapping regions:"); + $display("%2d (%2d): %x / %2d -- %x-%x", + i/M_REGIONS, i%M_REGIONS, + M_BASE_ADDR_INT[i], + M_ADDR_W_INT[i], + M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]), + M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i])) + ); + $display("%2d (%2d): %x / %2d -- %x-%x", + j/M_REGIONS, j%M_REGIONS, + M_BASE_ADDR_INT[j], + M_ADDR_W_INT[j], + M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j]), + M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j])) + ); + $error("Error: address ranges overlap (instance %m)"); + $finish; + end + end + end + end +end + +localparam logic [0:0] + STATE_IDLE = 1'd0, + STATE_DECODE = 1'd1; + +logic [0:0] state_reg = STATE_IDLE, state_next; + +logic s_axil_aready_reg = 1'b0, s_axil_aready_next; + +logic [SEL_W-1:0] m_select_reg = '0, m_select_next; +logic m_axil_avalid_reg = 1'b0, m_axil_avalid_next; +logic m_decerr_reg = 1'b0, m_decerr_next; +logic m_wc_valid_reg = 1'b0, m_wc_valid_next; +logic m_rc_valid_reg = 1'b0, m_rc_valid_next; + +assign s_axil_aready = s_axil_aready_reg; + +assign m_select = m_select_reg; +assign m_axil_avalid = m_axil_avalid_reg; + +assign m_wc_select = m_select_reg; +assign m_wc_decerr = m_decerr_reg; +assign m_wc_valid = m_wc_valid_reg; + +assign m_rc_select = m_select_reg; +assign m_rc_decerr = m_decerr_reg; +assign m_rc_valid = m_rc_valid_reg; + +logic match; + +always_comb begin + state_next = STATE_IDLE; + + match = 1'b0; + + s_axil_aready_next = 1'b0; + + m_select_next = m_select_reg; + m_axil_avalid_next = m_axil_avalid_reg && !m_axil_aready; + m_decerr_next = m_decerr_reg; + m_wc_valid_next = m_wc_valid_reg && !m_wc_ready; + m_rc_valid_next = m_rc_valid_reg && !m_rc_ready; + + case (state_reg) + STATE_IDLE: begin + // idle state, store values + s_axil_aready_next = 1'b0; + + if (s_axil_avalid && !s_axil_aready) begin + match = 1'b0; + for (integer i = 0; i < M_COUNT; i = i + 1) begin + for (integer j = 0; j < M_REGIONS; j = j + 1) begin + if (M_ADDR_W_INT[i*M_REGIONS+j] != 0 && (!M_SECURE_INT[i] || !s_axil_aprot[1]) && M_CONNECT_INT[i][S] && (s_axil_aaddr >> M_ADDR_W_INT[i*M_REGIONS+j]) == (M_BASE_ADDR_INT[i*M_REGIONS+j] >> M_ADDR_W_INT[i*M_REGIONS+j])) begin + m_select_next = SEL_W'(i); + match = 1'b1; + end + end + end + + if (match) begin + // address decode successful + m_axil_avalid_next = 1'b1; + m_decerr_next = 1'b0; + m_wc_valid_next = WC_OUTPUT; + m_rc_valid_next = 1'b1; + state_next = STATE_DECODE; + end else begin + // decode error + m_axil_avalid_next = 1'b0; + m_decerr_next = 1'b1; + m_wc_valid_next = WC_OUTPUT; + m_rc_valid_next = 1'b1; + state_next = STATE_DECODE; + end + end else begin + state_next = STATE_IDLE; + end + end + STATE_DECODE: begin + if (!m_axil_avalid_next && (!m_wc_valid_next || !WC_OUTPUT) && !m_rc_valid_next) begin + s_axil_aready_next = 1'b1; + state_next = STATE_IDLE; + end else begin + state_next = STATE_DECODE; + end + end + endcase +end + +always_ff @(posedge clk) begin + state_reg <= state_next; + s_axil_aready_reg <= s_axil_aready_next; + m_axil_avalid_reg <= m_axil_avalid_next; + m_wc_valid_reg <= m_wc_valid_next; + m_rc_valid_reg <= m_rc_valid_next; + + m_select_reg <= m_select_next; + m_decerr_reg <= m_decerr_next; + + if (rst) begin + state_reg <= STATE_IDLE; + s_axil_aready_reg <= 1'b0; + m_axil_avalid_reg <= 1'b0; + m_wc_valid_reg <= 1'b0; + m_rc_valid_reg <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/src/axi/rtl/taxi_axil_crossbar_rd.f b/src/axi/rtl/taxi_axil_crossbar_rd.f new file mode 100644 index 0000000..1a2db84 --- /dev/null +++ b/src/axi/rtl/taxi_axil_crossbar_rd.f @@ -0,0 +1,6 @@ +taxi_axil_crossbar_rd.sv +taxi_axil_crossbar_addr.sv +taxi_axil_register_rd.sv +taxi_axil_if.sv +../lib/taxi/src/prim/rtl/taxi_arbiter.sv +../lib/taxi/src/prim/rtl/taxi_penc.sv diff --git a/src/axi/rtl/taxi_axil_crossbar_rd.sv b/src/axi/rtl/taxi_axil_crossbar_rd.sv new file mode 100644 index 0000000..3b3edd6 --- /dev/null +++ b/src/axi/rtl/taxi_axil_crossbar_rd.sv @@ -0,0 +1,463 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2021-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 lite crossbar (read) + */ +module taxi_axil_crossbar_rd # +( + // Number of AXI inputs (slave interfaces) + parameter S_COUNT = 4, + // Number of AXI outputs (master interfaces) + parameter M_COUNT = 4, + // Address width in bits for address decoding + parameter ADDR_W = 32, + // TODO fix parametrization once verilator issue 5890 is fixed + // Number of concurrent operations for each slave interface + // S_COUNT concatenated fields of 32 bits + parameter S_ACCEPT = {S_COUNT{32'd16}}, + // Number of regions per master interface + parameter M_REGIONS = 1, + // Master interface base addresses + // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits + // set to zero for default addressing based on M_ADDR_W + parameter M_BASE_ADDR = '0, + // Master interface address widths + // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits + parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}}, + // Read connections between interfaces + // M_COUNT concatenated fields of S_COUNT bits + parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}}, + // Number of concurrent operations for each master interface + // M_COUNT concatenated fields of 32 bits + parameter M_ISSUE = {M_COUNT{32'd16}}, + // Secure master (fail operations based on awprot/arprot) + // M_COUNT bits + parameter M_SECURE = {M_COUNT{1'b0}}, + // Slave interface AR channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S_AR_REG_TYPE = {S_COUNT{2'd0}}, + // Slave interface R channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S_R_REG_TYPE = {S_COUNT{2'd2}}, + // Master interface AR channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M_AR_REG_TYPE = {M_COUNT{2'd1}}, + // Master interface R channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M_R_REG_TYPE = {M_COUNT{2'd0}} +) +( + input wire logic clk, + input wire logic rst, + + /* + * AXI4-lite slave interfaces + */ + taxi_axil_if.rd_slv s_axil_rd[S_COUNT], + + /* + * AXI4-lite master interfaces + */ + taxi_axil_if.rd_mst m_axil_rd[M_COUNT] +); + +// extract parameters +localparam DATA_W = s_axil_rd[0].DATA_W; +localparam S_ADDR_W = s_axil_rd[0].ADDR_W; +localparam STRB_W = s_axil_rd[0].STRB_W; +localparam logic ARUSER_EN = s_axil_rd[0].ARUSER_EN && m_axil_rd[0].ARUSER_EN; +localparam ARUSER_W = s_axil_rd[0].ARUSER_W; +localparam logic RUSER_EN = s_axil_rd[0].RUSER_EN && m_axil_rd[0].RUSER_EN; +localparam RUSER_W = s_axil_rd[0].RUSER_W; + +localparam CL_S_COUNT = $clog2(S_COUNT); +localparam CL_M_COUNT = $clog2(M_COUNT); +localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1; +localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1; + +localparam [S_COUNT-1:0][31:0] S_ACCEPT_INT = S_ACCEPT; +localparam [M_COUNT-1:0][31:0] M_ISSUE_INT = M_ISSUE; + +// check configuration +if (s_axil_rd[0].ADDR_W != ADDR_W) + $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)"); + +if (m_axil_rd[0].DATA_W != DATA_W) + $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)"); + +if (m_axil_rd[0].STRB_W != STRB_W) + $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)"); + +wire [ADDR_W-1:0] int_s_axil_araddr[S_COUNT]; +wire [2:0] int_s_axil_arprot[S_COUNT]; + +logic [M_COUNT-1:0] int_axil_arvalid[S_COUNT]; +logic [S_COUNT-1:0] int_axil_arready[M_COUNT]; + +wire [DATA_W-1:0] int_m_axil_rdata[M_COUNT]; +wire [1:0] int_m_axil_rresp[M_COUNT]; + +logic [S_COUNT-1:0] int_axil_rvalid[M_COUNT]; +logic [M_COUNT-1:0] int_axil_rready[S_COUNT]; + +for (genvar m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces + + taxi_axil_if #( + .DATA_W(s_axil_rd[0].DATA_W), + .ADDR_W(s_axil_rd[0].ADDR_W), + .STRB_W(s_axil_rd[0].STRB_W), + .AWUSER_EN(s_axil_rd[0].AWUSER_EN), + .AWUSER_W(s_axil_rd[0].AWUSER_W), + .WUSER_EN(s_axil_rd[0].WUSER_EN), + .WUSER_W(s_axil_rd[0].WUSER_W), + .BUSER_EN(s_axil_rd[0].BUSER_EN), + .BUSER_W(s_axil_rd[0].BUSER_W), + .ARUSER_EN(s_axil_rd[0].ARUSER_EN), + .ARUSER_W(s_axil_rd[0].ARUSER_W), + .RUSER_EN(s_axil_rd[0].RUSER_EN), + .RUSER_W(s_axil_rd[0].RUSER_W) + ) int_axil(); + + // S side register + taxi_axil_register_rd #( + .AR_REG_TYPE(S_AR_REG_TYPE[m*2 +: 2]), + .R_REG_TYPE(S_R_REG_TYPE[m*2 +: 2]) + ) + reg_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI4-Lite slave interface + */ + .s_axil_rd(s_axil_rd[m]), + + /* + * AXI4-Lite master interface + */ + .m_axil_rd(int_axil) + ); + + // response routing FIFO + localparam FIFO_AW = $clog2(S_ACCEPT_INT[m])+1; + + logic [FIFO_AW+1-1:0] fifo_wr_ptr_reg = 0; + logic [FIFO_AW+1-1:0] fifo_rd_ptr_reg = 0; + + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) + logic [CL_M_COUNT_INT-1:0] fifo_select[2**FIFO_AW]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) + logic fifo_decerr[2**FIFO_AW]; + + wire [CL_M_COUNT_INT-1:0] fifo_wr_select; + wire fifo_wr_decerr; + wire fifo_wr_en; + + logic [CL_M_COUNT_INT-1:0] fifo_rd_select_reg = 0; + logic fifo_rd_decerr_reg = 0; + logic fifo_rd_valid_reg = 0; + wire fifo_rd_en; + logic fifo_half_full_reg = 1'b0; + + wire fifo_empty = fifo_rd_ptr_reg == fifo_wr_ptr_reg; + + integer i; + + initial begin + for (i = 0; i < 2**FIFO_AW; i = i + 1) begin + fifo_select[i] = 0; + fifo_decerr[i] = 0; + end + end + + always_ff @(posedge clk) begin + if (fifo_wr_en) begin + fifo_select[fifo_wr_ptr_reg[FIFO_AW-1:0]] <= fifo_wr_select; + fifo_decerr[fifo_wr_ptr_reg[FIFO_AW-1:0]] <= fifo_wr_decerr; + fifo_wr_ptr_reg <= fifo_wr_ptr_reg + 1; + end + + fifo_rd_valid_reg <= fifo_rd_valid_reg && !fifo_rd_en; + + if ((fifo_rd_ptr_reg != fifo_wr_ptr_reg) && (!fifo_rd_valid_reg || fifo_rd_en)) begin + fifo_rd_select_reg <= fifo_select[fifo_rd_ptr_reg[FIFO_AW-1:0]]; + fifo_rd_decerr_reg <= fifo_decerr[fifo_rd_ptr_reg[FIFO_AW-1:0]]; + fifo_rd_valid_reg <= 1'b1; + fifo_rd_ptr_reg <= fifo_rd_ptr_reg + 1; + end + + fifo_half_full_reg <= $unsigned(fifo_wr_ptr_reg - fifo_rd_ptr_reg) >= 2**(FIFO_AW-1); + + if (rst) begin + fifo_wr_ptr_reg <= 0; + fifo_rd_ptr_reg <= 0; + fifo_rd_valid_reg <= 1'b0; + end + end + + // address decode and admission control + wire [CL_M_COUNT_INT-1:0] a_select; + + wire m_axil_avalid; + wire m_axil_aready; + + wire [CL_M_COUNT_INT-1:0] m_rc_select; + wire m_rc_decerr; + wire m_rc_valid; + wire m_rc_ready; + + taxi_axil_crossbar_addr #( + .S(m), + .S_COUNT(S_COUNT), + .M_COUNT(M_COUNT), + .SEL_W(CL_M_COUNT_INT), + .ADDR_W(ADDR_W), + .STRB_W(STRB_W), + .M_REGIONS(M_REGIONS), + .M_BASE_ADDR(M_BASE_ADDR), + .M_ADDR_W(M_ADDR_W), + .M_CONNECT(M_CONNECT), + .M_SECURE(M_SECURE), + .WC_OUTPUT(0) + ) + addr_inst ( + .clk(clk), + .rst(rst), + + /* + * Address input + */ + .s_axil_aaddr(int_axil.araddr), + .s_axil_aprot(int_axil.arprot), + .s_axil_avalid(int_axil.arvalid), + .s_axil_aready(int_axil.arready), + + /* + * Address output + */ + .m_select(a_select), + .m_axil_avalid(m_axil_avalid), + .m_axil_aready(m_axil_aready), + + /* + * Write command output + */ + .m_wc_select(), + .m_wc_decerr(), + .m_wc_valid(), + .m_wc_ready(1'b1), + + /* + * Response command output + */ + .m_rc_select(m_rc_select), + .m_rc_decerr(m_rc_decerr), + .m_rc_valid(m_rc_valid), + .m_rc_ready(m_rc_ready) + ); + + assign int_s_axil_araddr[m] = int_axil.araddr; + assign int_s_axil_arprot[m] = int_axil.arprot; + + always_comb begin + int_axil_arvalid[m] = '0; + int_axil_arvalid[m][a_select] = m_axil_avalid; + end + assign m_axil_aready = int_axil_arready[a_select][m]; + + // response handling + assign fifo_wr_select = m_rc_select; + assign fifo_wr_decerr = m_rc_decerr; + assign fifo_wr_en = m_rc_valid && !fifo_half_full_reg; + assign m_rc_ready = !fifo_half_full_reg; + + // write response handling + wire [CL_M_COUNT_INT-1:0] r_select = M_COUNT > 1 ? fifo_rd_select_reg : '0; + wire r_decerr = fifo_rd_decerr_reg; + wire r_valid = fifo_rd_valid_reg; + + // read response mux + assign int_axil.rdata = r_decerr ? '0 : int_m_axil_rdata[r_select]; + assign int_axil.rresp = r_decerr ? 2'b11 : int_m_axil_rresp[r_select]; + assign int_axil.rvalid = (r_decerr ? 1'b1 : int_axil_rvalid[r_select][m]) && r_valid; + + always_comb begin + int_axil_rready[m] = '0; + int_axil_rready[m][r_select] = r_valid && int_axil.rready; + end + + assign fifo_rd_en = int_axil.rvalid && int_axil.rready && r_valid; + +end // s_ifaces + +for (genvar n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces + + taxi_axil_if #( + .DATA_W(m_axil_rd[0].DATA_W), + .ADDR_W(m_axil_rd[0].ADDR_W), + .STRB_W(m_axil_rd[0].STRB_W), + .AWUSER_EN(m_axil_rd[0].AWUSER_EN), + .AWUSER_W(m_axil_rd[0].AWUSER_W), + .WUSER_EN(m_axil_rd[0].WUSER_EN), + .WUSER_W(m_axil_rd[0].WUSER_W), + .BUSER_EN(m_axil_rd[0].BUSER_EN), + .BUSER_W(m_axil_rd[0].BUSER_W), + .ARUSER_EN(m_axil_rd[0].ARUSER_EN), + .ARUSER_W(m_axil_rd[0].ARUSER_W), + .RUSER_EN(m_axil_rd[0].RUSER_EN), + .RUSER_W(m_axil_rd[0].RUSER_W) + ) int_axil(); + + // response routing FIFO + localparam FIFO_AW = $clog2(M_ISSUE_INT[n])+1; + + logic [FIFO_AW+1-1:0] fifo_wr_ptr_reg = '0; + logic [FIFO_AW+1-1:0] fifo_rd_ptr_reg = '0; + + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) + logic [CL_S_COUNT_INT-1:0] fifo_select[2**FIFO_AW]; + wire [CL_S_COUNT_INT-1:0] fifo_wr_select; + wire fifo_wr_en; + wire fifo_rd_en; + logic fifo_half_full_reg = 1'b0; + + wire fifo_empty = fifo_rd_ptr_reg == fifo_wr_ptr_reg; + + initial begin + for (integer i = 0; i < 2**FIFO_AW; i = i + 1) begin + fifo_select[i] = '0; + end + end + + always_ff @(posedge clk) begin + if (fifo_wr_en) begin + fifo_select[fifo_wr_ptr_reg[FIFO_AW-1:0]] <= fifo_wr_select; + fifo_wr_ptr_reg <= fifo_wr_ptr_reg + 1; + end + if (fifo_rd_en) begin + fifo_rd_ptr_reg <= fifo_rd_ptr_reg + 1; + end + + fifo_half_full_reg <= $unsigned(fifo_wr_ptr_reg - fifo_rd_ptr_reg) >= 2**(FIFO_AW-1); + + if (rst) begin + fifo_wr_ptr_reg <= '0; + fifo_rd_ptr_reg <= '0; + end + end + + // address arbitration + wire [S_COUNT-1:0] a_req; + wire [S_COUNT-1:0] a_ack; + wire [S_COUNT-1:0] a_grant; + wire a_grant_valid; + wire [CL_S_COUNT_INT-1:0] a_grant_index; + + if (S_COUNT > 1) begin : arb + + taxi_arbiter #( + .PORTS(S_COUNT), + .ARB_ROUND_ROBIN(1), + .ARB_BLOCK(1), + .ARB_BLOCK_ACK(1), + .LSB_HIGH_PRIO(1) + ) + a_arb_inst ( + .clk(clk), + .rst(rst), + .req(a_req), + .ack(a_ack), + .grant(a_grant), + .grant_valid(a_grant_valid), + .grant_index(a_grant_index) + ); + + end else begin + + logic grant_valid_reg = 1'b0; + + always @(posedge clk) begin + if (a_req) begin + grant_valid_reg <= 1'b1; + end + + if (a_ack || rst) begin + grant_valid_reg <= 1'b0; + end + end + + assign a_grant_valid = grant_valid_reg; + assign a_grant = grant_valid_reg; + assign a_grant_index = '0; + + end + + // address mux + assign int_axil.araddr = int_s_axil_araddr[a_grant_index]; + assign int_axil.arprot = int_s_axil_arprot[a_grant_index]; + assign int_axil.arvalid = int_axil_arvalid[a_grant_index][n] && a_grant_valid; + + always_comb begin + int_axil_arready[n] = '0; + int_axil_arready[n][a_grant_index] = a_grant_valid && int_axil.arready; + end + + for (genvar m = 0; m < S_COUNT; m = m + 1) begin + assign a_req[m] = int_axil_arvalid[m][n] && !a_grant_valid && !fifo_half_full_reg; + assign a_ack[m] = a_grant[m] && int_axil_arvalid[m][n] && int_axil.arready; + end + + assign fifo_wr_select = a_grant_index; + assign fifo_wr_en = int_axil.arvalid && int_axil.arready && a_grant_valid; + + // read response forwarding + wire [CL_S_COUNT_INT-1:0] r_select = S_COUNT > 1 ? fifo_select[fifo_rd_ptr_reg[FIFO_AW-1:0]] : '0; + + assign int_m_axil_rdata[n] = int_axil.rdata; + assign int_m_axil_rresp[n] = int_axil.rresp; + + always_comb begin + int_axil_rvalid[n] = '0; + int_axil_rvalid[n][r_select] = int_axil.rvalid; + end + assign int_axil.rready = int_axil_rready[r_select][n]; + + assign fifo_rd_en = int_axil.rvalid && int_axil.rready; + + // M side register + taxi_axil_register_rd #( + .AR_REG_TYPE(M_AR_REG_TYPE[n*2 +: 2]), + .R_REG_TYPE(M_R_REG_TYPE[n*2 +: 2]) + ) + reg_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI4-Lite slave interface + */ + .s_axil_rd(int_axil), + + /* + * AXI4-Lite master interface + */ + .m_axil_rd(m_axil_rd[n]) + ); + +end // m_ifaces + +endmodule + +`resetall diff --git a/src/axi/rtl/taxi_axil_crossbar_wr.f b/src/axi/rtl/taxi_axil_crossbar_wr.f new file mode 100644 index 0000000..4c10f99 --- /dev/null +++ b/src/axi/rtl/taxi_axil_crossbar_wr.f @@ -0,0 +1,6 @@ +taxi_axil_crossbar_wr.sv +taxi_axil_crossbar_addr.sv +taxi_axil_register_wr.sv +taxi_axil_if.sv +../lib/taxi/src/prim/rtl/taxi_arbiter.sv +../lib/taxi/src/prim/rtl/taxi_penc.sv diff --git a/src/axi/rtl/taxi_axil_crossbar_wr.sv b/src/axi/rtl/taxi_axil_crossbar_wr.sv new file mode 100644 index 0000000..911607b --- /dev/null +++ b/src/axi/rtl/taxi_axil_crossbar_wr.sv @@ -0,0 +1,556 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2021-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 lite crossbar (write) + */ +module taxi_axil_crossbar_wr # +( + // Number of AXI inputs (slave interfaces) + parameter S_COUNT = 4, + // Number of AXI outputs (master interfaces) + parameter M_COUNT = 4, + // Address width in bits for address decoding + parameter ADDR_W = 32, + // TODO fix parametrization once verilator issue 5890 is fixed + // Number of concurrent operations for each slave interface + // S_COUNT concatenated fields of 32 bits + parameter S_ACCEPT = {S_COUNT{32'd16}}, + // Number of regions per master interface + parameter M_REGIONS = 1, + // Master interface base addresses + // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits + // set to zero for default addressing based on M_ADDR_W + parameter M_BASE_ADDR = 0, + // Master interface address widths + // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits + parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}}, + // Write connections between interfaces + // M_COUNT concatenated fields of S_COUNT bits + parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}}, + // Number of concurrent operations for each master interface + // M_COUNT concatenated fields of 32 bits + parameter M_ISSUE = {M_COUNT{32'd16}}, + // Secure master (fail operations based on awprot/arprot) + // M_COUNT bits + parameter M_SECURE = {M_COUNT{1'b0}}, + // Slave interface AW channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S_AW_REG_TYPE = {S_COUNT{2'd0}}, + // Slave interface W channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S_W_REG_TYPE = {S_COUNT{2'd0}}, + // Slave interface B channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter S_B_REG_TYPE = {S_COUNT{2'd1}}, + // Master interface AW channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M_AW_REG_TYPE = {M_COUNT{2'd1}}, + // Master interface W channel register type (output) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M_W_REG_TYPE = {M_COUNT{2'd2}}, + // Master interface B channel register type (input) + // 0 to bypass, 1 for simple buffer, 2 for skid buffer + parameter M_B_REG_TYPE = {M_COUNT{2'd0}} +) +( + input wire logic clk, + input wire logic rst, + + /* + * AXI4-lite slave interfaces + */ + taxi_axil_if.wr_slv s_axil_wr[S_COUNT], + + /* + * AXI4-lite master interfaces + */ + taxi_axil_if.wr_mst m_axil_wr[M_COUNT] +); + +// extract parameters +localparam DATA_W = s_axil_wr[0].DATA_W; +localparam S_ADDR_W = s_axil_wr[0].ADDR_W; +localparam STRB_W = s_axil_wr[0].STRB_W; +localparam logic AWUSER_EN = s_axil_wr[0].AWUSER_EN && m_axil_wr[0].AWUSER_EN; +localparam AWUSER_W = s_axil_wr[0].AWUSER_W; +localparam logic WUSER_EN = s_axil_wr[0].WUSER_EN && m_axil_wr[0].WUSER_EN; +localparam WUSER_W = s_axil_wr[0].WUSER_W; +localparam logic BUSER_EN = s_axil_wr[0].BUSER_EN && m_axil_wr[0].BUSER_EN; +localparam BUSER_W = s_axil_wr[0].BUSER_W; + +localparam CL_S_COUNT = $clog2(S_COUNT); +localparam CL_M_COUNT = $clog2(M_COUNT); +localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1; +localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1; + +localparam [S_COUNT-1:0][31:0] S_ACCEPT_INT = S_ACCEPT; +localparam [M_COUNT-1:0][31:0] M_ISSUE_INT = M_ISSUE; + +// check configuration +if (s_axil_wr[0].ADDR_W != ADDR_W) + $fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)"); + +if (m_axil_wr[0].DATA_W != DATA_W) + $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)"); + +if (m_axil_wr[0].STRB_W != STRB_W) + $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)"); + +wire [ADDR_W-1:0] int_s_axil_awaddr[S_COUNT]; +wire [2:0] int_s_axil_awprot[S_COUNT]; + +logic [M_COUNT-1:0] int_axil_awvalid[S_COUNT]; +logic [S_COUNT-1:0] int_axil_awready[M_COUNT]; + +wire [DATA_W-1:0] int_s_axil_wdata[S_COUNT]; +wire [STRB_W-1:0] int_s_axil_wstrb[S_COUNT]; + +logic [M_COUNT-1:0] int_axil_wvalid[S_COUNT]; +logic [S_COUNT-1:0] int_axil_wready[M_COUNT]; + +wire [1:0] int_m_axil_bresp[M_COUNT]; + +logic [S_COUNT-1:0] int_axil_bvalid[M_COUNT]; +logic [M_COUNT-1:0] int_axil_bready[S_COUNT]; + +for (genvar m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces + + taxi_axil_if #( + .DATA_W(s_axil_wr[0].DATA_W), + .ADDR_W(s_axil_wr[0].ADDR_W), + .STRB_W(s_axil_wr[0].STRB_W), + .AWUSER_EN(s_axil_wr[0].AWUSER_EN), + .AWUSER_W(s_axil_wr[0].AWUSER_W), + .WUSER_EN(s_axil_wr[0].WUSER_EN), + .WUSER_W(s_axil_wr[0].WUSER_W), + .BUSER_EN(s_axil_wr[0].BUSER_EN), + .BUSER_W(s_axil_wr[0].BUSER_W), + .ARUSER_EN(s_axil_wr[0].ARUSER_EN), + .ARUSER_W(s_axil_wr[0].ARUSER_W), + .RUSER_EN(s_axil_wr[0].RUSER_EN), + .RUSER_W(s_axil_wr[0].RUSER_W) + ) int_axil(); + + // S side register + taxi_axil_register_wr #( + .AW_REG_TYPE(S_AW_REG_TYPE[m*2 +: 2]), + .W_REG_TYPE(S_W_REG_TYPE[m*2 +: 2]), + .B_REG_TYPE(S_B_REG_TYPE[m*2 +: 2]) + ) + reg_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI4-Lite slave interface + */ + .s_axil_wr(s_axil_wr[m]), + + /* + * AXI4-Lite master interface + */ + .m_axil_wr(int_axil) + ); + + // response routing FIFO + localparam FIFO_AW = $clog2(S_ACCEPT_INT[m])+1; + + logic [FIFO_AW+1-1:0] fifo_wr_ptr_reg = '0; + logic [FIFO_AW+1-1:0] fifo_rd_ptr_reg = '0; + + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) + logic [CL_M_COUNT_INT-1:0] fifo_select[2**FIFO_AW]; + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) + logic fifo_decerr[2**FIFO_AW]; + + wire [CL_M_COUNT_INT-1:0] fifo_wr_select; + wire fifo_wr_decerr; + wire fifo_wr_en; + + logic [CL_M_COUNT_INT-1:0] fifo_rd_select_reg = '0; + logic fifo_rd_decerr_reg = 1'b0; + logic fifo_rd_valid_reg = 1'b0; + wire fifo_rd_en; + logic fifo_half_full_reg = 1'b0; + + wire fifo_empty = fifo_rd_ptr_reg == fifo_wr_ptr_reg; + + initial begin + for (integer i = 0; i < 2**FIFO_AW; i = i + 1) begin + fifo_select[i] = '0; + fifo_decerr[i] = '0; + end + end + + always_ff @(posedge clk) begin + if (fifo_wr_en) begin + fifo_select[fifo_wr_ptr_reg[FIFO_AW-1:0]] <= fifo_wr_select; + fifo_decerr[fifo_wr_ptr_reg[FIFO_AW-1:0]] <= fifo_wr_decerr; + fifo_wr_ptr_reg <= fifo_wr_ptr_reg + 1; + end + + fifo_rd_valid_reg <= fifo_rd_valid_reg && !fifo_rd_en; + + if ((fifo_rd_ptr_reg != fifo_wr_ptr_reg) && (!fifo_rd_valid_reg || fifo_rd_en)) begin + fifo_rd_select_reg <= fifo_select[fifo_rd_ptr_reg[FIFO_AW-1:0]]; + fifo_rd_decerr_reg <= fifo_decerr[fifo_rd_ptr_reg[FIFO_AW-1:0]]; + fifo_rd_valid_reg <= 1'b1; + fifo_rd_ptr_reg <= fifo_rd_ptr_reg + 1; + end + + fifo_half_full_reg <= $unsigned(fifo_wr_ptr_reg - fifo_rd_ptr_reg) >= 2**(FIFO_AW-1); + + if (rst) begin + fifo_wr_ptr_reg <= '0; + fifo_rd_ptr_reg <= '0; + fifo_rd_valid_reg <= 1'b0; + end + end + + // address decode and admission control + wire [CL_M_COUNT_INT-1:0] a_select; + + wire m_axil_avalid; + wire m_axil_aready; + + wire [CL_M_COUNT_INT-1:0] m_wc_select; + wire m_wc_decerr; + wire m_wc_valid; + wire m_wc_ready; + + wire [CL_M_COUNT_INT-1:0] m_rc_select; + wire m_rc_decerr; + wire m_rc_valid; + wire m_rc_ready; + + taxi_axil_crossbar_addr #( + .S(m), + .S_COUNT(S_COUNT), + .M_COUNT(M_COUNT), + .SEL_W(CL_M_COUNT_INT), + .ADDR_W(ADDR_W), + .STRB_W(STRB_W), + .M_REGIONS(M_REGIONS), + .M_BASE_ADDR(M_BASE_ADDR), + .M_ADDR_W(M_ADDR_W), + .M_CONNECT(M_CONNECT), + .M_SECURE(M_SECURE), + .WC_OUTPUT(1) + ) + addr_inst ( + .clk(clk), + .rst(rst), + + /* + * Address input + */ + .s_axil_aaddr(int_axil.awaddr), + .s_axil_aprot(int_axil.awprot), + .s_axil_avalid(int_axil.awvalid), + .s_axil_aready(int_axil.awready), + + /* + * Address output + */ + .m_select(a_select), + .m_axil_avalid(m_axil_avalid), + .m_axil_aready(m_axil_aready), + + /* + * Write command output + */ + .m_wc_select(m_wc_select), + .m_wc_decerr(m_wc_decerr), + .m_wc_valid(m_wc_valid), + .m_wc_ready(m_wc_ready), + + /* + * Response command output + */ + .m_rc_select(m_rc_select), + .m_rc_decerr(m_rc_decerr), + .m_rc_valid(m_rc_valid), + .m_rc_ready(m_rc_ready) + ); + + assign int_s_axil_awaddr[m] = int_axil.awaddr; + assign int_s_axil_awprot[m] = int_axil.awprot; + + always_comb begin + int_axil_awvalid[m] = '0; + int_axil_awvalid[m][a_select] = m_axil_avalid; + end + assign m_axil_aready = int_axil_awready[a_select][m]; + + // write command handling + logic [CL_M_COUNT_INT-1:0] w_select_reg = '0, w_select_next; + logic w_drop_reg = 1'b0, w_drop_next; + logic w_select_valid_reg = 1'b0, w_select_valid_next; + + assign m_wc_ready = !w_select_valid_reg; + + always_comb begin + w_select_next = w_select_reg; + w_drop_next = w_drop_reg && !(int_axil.wvalid && int_axil.wready); + w_select_valid_next = w_select_valid_reg && !(int_axil.wvalid && int_axil.wready); + + if (m_wc_valid && !w_select_valid_reg) begin + w_select_next = m_wc_select; + w_drop_next = m_wc_decerr; + w_select_valid_next = m_wc_valid; + end + end + + always_ff @(posedge clk) begin + w_select_valid_reg <= w_select_valid_next; + w_select_reg <= w_select_next; + w_drop_reg <= w_drop_next; + + if (rst) begin + w_select_valid_reg <= 1'b0; + end + end + + // write data forwarding + assign int_s_axil_wdata[m] = int_axil.wdata; + assign int_s_axil_wstrb[m] = int_axil.wstrb; + + always_comb begin + int_axil_wvalid[m] = '0; + int_axil_wvalid[m][w_select_reg] = int_axil.wvalid && w_select_valid_reg && !w_drop_reg; + end + assign int_axil.wready = int_axil_wready[w_select_reg][m] || w_drop_reg; + + // response handling + assign fifo_wr_select = m_rc_select; + assign fifo_wr_decerr = m_rc_decerr; + assign fifo_wr_en = m_rc_valid && !fifo_half_full_reg; + assign m_rc_ready = !fifo_half_full_reg; + + // write response handling + wire [CL_M_COUNT_INT-1:0] b_select = M_COUNT > 1 ? fifo_rd_select_reg : '0; + wire b_decerr = fifo_rd_decerr_reg; + wire b_valid = fifo_rd_valid_reg; + + // write response mux + assign int_axil.bresp = b_decerr ? 2'b11 : int_m_axil_bresp[b_select]; + assign int_axil.bvalid = (b_decerr ? 1'b1 : int_axil_bvalid[b_select][m]) && b_valid; + + always_comb begin + int_axil_bready[m] = '0; + int_axil_bready[m][b_select] = b_valid && int_axil.bready; + end + + assign fifo_rd_en = int_axil.bvalid && int_axil.bready && b_valid; + +end // s_ifaces + +for (genvar n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces + + taxi_axil_if #( + .DATA_W(m_axil_wr[0].DATA_W), + .ADDR_W(m_axil_wr[0].ADDR_W), + .STRB_W(m_axil_wr[0].STRB_W), + .AWUSER_EN(m_axil_wr[0].AWUSER_EN), + .AWUSER_W(m_axil_wr[0].AWUSER_W), + .WUSER_EN(m_axil_wr[0].WUSER_EN), + .WUSER_W(m_axil_wr[0].WUSER_W), + .BUSER_EN(m_axil_wr[0].BUSER_EN), + .BUSER_W(m_axil_wr[0].BUSER_W), + .ARUSER_EN(m_axil_wr[0].ARUSER_EN), + .ARUSER_W(m_axil_wr[0].ARUSER_W), + .RUSER_EN(m_axil_wr[0].RUSER_EN), + .RUSER_W(m_axil_wr[0].RUSER_W) + ) int_axil(); + + // response routing FIFO + localparam FIFO_AW = $clog2(M_ISSUE_INT[n])+1; + + logic [FIFO_AW+1-1:0] fifo_wr_ptr_reg = '0; + logic [FIFO_AW+1-1:0] fifo_rd_ptr_reg = '0; + + (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) + logic [CL_S_COUNT_INT-1:0] fifo_select[2**FIFO_AW]; + wire [CL_S_COUNT_INT-1:0] fifo_wr_select; + wire fifo_wr_en; + wire fifo_rd_en; + logic fifo_half_full_reg = 1'b0; + + wire fifo_empty = fifo_rd_ptr_reg == fifo_wr_ptr_reg; + + initial begin + for (integer i = 0; i < 2**FIFO_AW; i = i + 1) begin + fifo_select[i] = '0; + end + end + + always_ff @(posedge clk) begin + if (fifo_wr_en) begin + fifo_select[fifo_wr_ptr_reg[FIFO_AW-1:0]] <= fifo_wr_select; + fifo_wr_ptr_reg <= fifo_wr_ptr_reg + 1; + end + if (fifo_rd_en) begin + fifo_rd_ptr_reg <= fifo_rd_ptr_reg + 1; + end + + fifo_half_full_reg <= $unsigned(fifo_wr_ptr_reg - fifo_rd_ptr_reg) >= 2**(FIFO_AW-1); + + if (rst) begin + fifo_wr_ptr_reg <= '0; + fifo_rd_ptr_reg <= '0; + end + end + + // address arbitration + logic [CL_S_COUNT_INT-1:0] w_select_reg = '0, w_select_next; + logic w_select_valid_reg = 1'b0, w_select_valid_next; + logic w_select_new_reg = 1'b0, w_select_new_next; + + wire [S_COUNT-1:0] a_req; + wire [S_COUNT-1:0] a_ack; + wire [S_COUNT-1:0] a_grant; + wire a_grant_valid; + wire [CL_S_COUNT_INT-1:0] a_grant_index; + + if (S_COUNT > 1) begin : arb + + taxi_arbiter #( + .PORTS(S_COUNT), + .ARB_ROUND_ROBIN(1), + .ARB_BLOCK(1), + .ARB_BLOCK_ACK(1), + .LSB_HIGH_PRIO(1) + ) + a_arb_inst ( + .clk(clk), + .rst(rst), + .req(a_req), + .ack(a_ack), + .grant(a_grant), + .grant_valid(a_grant_valid), + .grant_index(a_grant_index) + ); + + end else begin + + logic grant_valid_reg = 1'b0; + + always @(posedge clk) begin + if (a_req) begin + grant_valid_reg <= 1'b1; + end + + if (a_ack || rst) begin + grant_valid_reg <= 1'b0; + end + end + + assign a_grant_valid = grant_valid_reg; + assign a_grant = grant_valid_reg; + assign a_grant_index = '0; + + end + + // address mux + assign int_axil.awaddr = int_s_axil_awaddr[a_grant_index]; + assign int_axil.awprot = int_s_axil_awprot[a_grant_index]; + assign int_axil.awvalid = int_axil_awvalid[a_grant_index][n] && a_grant_valid; + + always_comb begin + int_axil_awready[n] = '0; + int_axil_awready[n][a_grant_index] = a_grant_valid && int_axil.awready; + end + + for (genvar m = 0; m < S_COUNT; m = m + 1) begin + assign a_req[m] = int_axil_awvalid[m][n] && !a_grant_valid && !fifo_half_full_reg && !w_select_valid_next; + assign a_ack[m] = a_grant[m] && int_axil_awvalid[m][n] && int_axil.awready; + end + + assign fifo_wr_select = a_grant_index; + assign fifo_wr_en = int_axil.awvalid && int_axil.awready && a_grant_valid; + + // write data mux + assign int_axil.wdata = int_s_axil_wdata[w_select_reg]; + assign int_axil.wstrb = int_s_axil_wstrb[w_select_reg]; + assign int_axil.wvalid = int_axil_wvalid[w_select_reg][n] && w_select_valid_reg; + + always_comb begin + int_axil_wready[n] = '0; + int_axil_wready[n][w_select_reg] = w_select_valid_reg && int_axil.wready; + end + + // write data routing + always_comb begin + w_select_next = w_select_reg; + w_select_valid_next = w_select_valid_reg && !(int_axil.wvalid && int_axil.wready); + w_select_new_next = w_select_new_reg || a_grant_valid == 0 || a_ack != 0; + + if (a_grant_valid && !w_select_valid_reg && w_select_new_reg) begin + w_select_next = a_grant_index; + w_select_valid_next = a_grant_valid; + w_select_new_next = 1'b0; + end + end + + always_ff @(posedge clk) begin + w_select_reg <= w_select_next; + w_select_valid_reg <= w_select_valid_next; + w_select_new_reg <= w_select_new_next; + + if (rst) begin + w_select_valid_reg <= 1'b0; + w_select_new_reg <= 1'b1; + end + end + + // write response forwarding + wire [CL_S_COUNT_INT-1:0] b_select = S_COUNT > 1 ? fifo_select[fifo_rd_ptr_reg[FIFO_AW-1:0]] : '0; + + assign int_m_axil_bresp[n] = int_axil.bresp; + + always_comb begin + int_axil_bvalid[n] = '0; + int_axil_bvalid[n][b_select] = int_axil.bvalid; + end + assign int_axil.bready = int_axil_bready[b_select][n]; + + assign fifo_rd_en = int_axil.bvalid && int_axil.bready; + + // M side register + taxi_axil_register_wr #( + .AW_REG_TYPE(M_AW_REG_TYPE[n*2 +: 2]), + .W_REG_TYPE(M_W_REG_TYPE[n*2 +: 2]), + .B_REG_TYPE(M_B_REG_TYPE[n*2 +: 2]) + ) + reg_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI4-Lite slave interface + */ + .s_axil_wr(int_axil), + + /* + * AXI4-Lite master interface + */ + .m_axil_wr(m_axil_wr[n]) + ); + +end // m_ifaces + +endmodule + +`resetall diff --git a/src/axi/tb/taxi_axil_crossbar/Makefile b/src/axi/tb/taxi_axil_crossbar/Makefile new file mode 100644 index 0000000..804b73b --- /dev/null +++ b/src/axi/tb/taxi_axil_crossbar/Makefile @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2020-2025 +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +DUT = taxi_axil_crossbar +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = test_$(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +REG_TYPE ?= 1 + +# module parameters +export PARAM_DATA_W := 32 +export PARAM_ADDR_W := 32 +export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 ) +export PARAM_AWUSER_EN := 0 +export PARAM_AWUSER_W := 1 +export PARAM_WUSER_EN := 0 +export PARAM_WUSER_W := 1 +export PARAM_BUSER_EN := 0 +export PARAM_BUSER_W := 1 +export PARAM_ARUSER_EN := 0 +export PARAM_ARUSER_W := 1 +export PARAM_RUSER_EN := 0 +export PARAM_RUSER_W := 1 +export PARAM_M_REGIONS := 1 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += -Wno-WIDTH + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/src/axi/tb/taxi_axil_crossbar/test_taxi_axil_crossbar.py b/src/axi/tb/taxi_axil_crossbar/test_taxi_axil_crossbar.py new file mode 100644 index 0000000..1b85990 --- /dev/null +++ b/src/axi/tb/taxi_axil_crossbar/test_taxi_axil_crossbar.py @@ -0,0 +1,260 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: CERN-OHL-S-2.0 +""" + +Copyright (c) 2020-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import itertools +import logging +import os +import random + +import cocotb_test.simulator +import pytest + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotb.regression import TestFactory + +from cocotbext.axi import AxiLiteBus, AxiLiteMaster, AxiLiteRam + + +class TB(object): + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 10, units="ns").start()) + + self.axil_master = [AxiLiteMaster(AxiLiteBus.from_entity(ch), dut.clk, dut.rst) for ch in dut.s_axil] + self.axil_ram = [AxiLiteRam(AxiLiteBus.from_entity(ch), dut.clk, dut.rst, size=2**16) for ch in dut.m_axil] + + def set_idle_generator(self, generator=None): + if generator: + for master in self.axil_master: + master.write_if.aw_channel.set_pause_generator(generator()) + master.write_if.w_channel.set_pause_generator(generator()) + master.read_if.ar_channel.set_pause_generator(generator()) + for ram in self.axil_ram: + ram.write_if.b_channel.set_pause_generator(generator()) + ram.read_if.r_channel.set_pause_generator(generator()) + + def set_backpressure_generator(self, generator=None): + if generator: + for master in self.axil_master: + master.write_if.b_channel.set_pause_generator(generator()) + master.read_if.r_channel.set_pause_generator(generator()) + for ram in self.axil_ram: + ram.write_if.aw_channel.set_pause_generator(generator()) + ram.write_if.w_channel.set_pause_generator(generator()) + ram.read_if.ar_channel.set_pause_generator(generator()) + + async def cycle_reset(self): + self.dut.rst.setimmediatevalue(0) + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 1 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 0 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + +async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, s=0, m=0): + + tb = TB(dut) + + byte_lanes = tb.axil_master[s].write_if.byte_lanes + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + for length in range(1, byte_lanes*2): + for offset in range(byte_lanes): + tb.log.info("length %d, offset %d", length, offset) + ram_addr = offset+0x1000 + addr = ram_addr + m*0x1000000 + test_data = bytearray([x % 256 for x in range(length)]) + + tb.axil_ram[m].write(ram_addr-128, b'\xaa'*(length+256)) + + await tb.axil_master[s].write(addr, test_data) + + tb.log.debug("%s", tb.axil_ram[m].hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48)) + + assert tb.axil_ram[m].read(ram_addr, length) == test_data + assert tb.axil_ram[m].read(ram_addr-1, 1) == b'\xaa' + assert tb.axil_ram[m].read(ram_addr+length, 1) == b'\xaa' + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, s=0, m=0): + + tb = TB(dut) + + byte_lanes = tb.axil_master[s].write_if.byte_lanes + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + for length in range(1, byte_lanes*2): + for offset in range(byte_lanes): + tb.log.info("length %d, offset %d", length, offset) + ram_addr = offset+0x1000 + addr = ram_addr + m*0x1000000 + test_data = bytearray([x % 256 for x in range(length)]) + + tb.axil_ram[m].write(ram_addr, test_data) + + data = await tb.axil_master[s].read(addr, length) + + assert data.data == test_data + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + async def worker(master, offset, aperture, count=16): + for k in range(count): + m = random.randrange(len(tb.axil_ram)) + length = random.randint(1, min(32, aperture)) + addr = offset+random.randint(0, aperture-length) + m*0x1000000 + test_data = bytearray([x % 256 for x in range(length)]) + + await Timer(random.randint(1, 100), 'ns') + + await master.write(addr, test_data) + + await Timer(random.randint(1, 100), 'ns') + + data = await master.read(addr, length) + assert data.data == test_data + + workers = [] + + for k in range(16): + workers.append(cocotb.start_soon(worker(tb.axil_master[k % len(tb.axil_master)], k*0x1000, 0x1000, count=16))) + + while workers: + await workers.pop(0).join() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +if getattr(cocotb, 'top', None) is not None: + + s_count = len(cocotb.top.s_axil) + m_count = len(cocotb.top.m_axil) + + for test in [run_test_write, run_test_read]: + + factory = TestFactory(test) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) + factory.add_option("s", range(min(s_count, 2))) + factory.add_option("m", range(min(m_count, 2))) + factory.generate_tests() + + factory = TestFactory(run_stress_test) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +@pytest.mark.parametrize("data_w", [8, 16, 32]) +@pytest.mark.parametrize("m_count", [1, 4]) +@pytest.mark.parametrize("s_count", [1, 4]) +def test_taxi_axil_crossbar(request, s_count, m_count, data_w): + dut = "taxi_axil_crossbar" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = module + + verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.sv"), + os.path.join(rtl_dir, f"{dut}.f"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['S_COUNT'] = s_count + parameters['M_COUNT'] = m_count + parameters['DATA_W'] = data_w + parameters['ADDR_W'] = 32 + parameters['STRB_W'] = parameters['DATA_W'] // 8 + parameters['AWUSER_EN'] = 0 + parameters['AWUSER_W'] = 1 + parameters['WUSER_EN'] = 0 + parameters['WUSER_W'] = 1 + parameters['BUSER_EN'] = 0 + parameters['BUSER_W'] = 1 + parameters['ARUSER_EN'] = 0 + parameters['ARUSER_W'] = 1 + parameters['RUSER_EN'] = 0 + parameters['RUSER_W'] = 1 + parameters['M_REGIONS'] = 1 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/src/axi/tb/taxi_axil_crossbar/test_taxi_axil_crossbar.sv b/src/axi/tb/taxi_axil_crossbar/test_taxi_axil_crossbar.sv new file mode 100644 index 0000000..517b6bf --- /dev/null +++ b/src/axi/tb/taxi_axil_crossbar/test_taxi_axil_crossbar.sv @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4-lite crossbar testbench + */ +module test_taxi_axil_crossbar # +( + /* verilator lint_off WIDTHTRUNC */ + parameter S_COUNT = 4, + parameter M_COUNT = 4, + parameter DATA_W = 32, + parameter ADDR_W = 32, + parameter STRB_W = (DATA_W/8), + parameter logic AWUSER_EN = 1'b0, + parameter AWUSER_W = 1, + parameter logic WUSER_EN = 1'b0, + parameter WUSER_W = 1, + parameter logic BUSER_EN = 1'b0, + parameter BUSER_W = 1, + parameter logic ARUSER_EN = 1'b0, + parameter ARUSER_W = 1, + parameter logic RUSER_EN = 1'b0, + parameter RUSER_W = 1, + parameter S_ACCEPT = {S_COUNT{32'd16}}, + parameter M_REGIONS = 1, + parameter M_BASE_ADDR = '0, + parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}}, + parameter M_CONNECT_RD = {M_COUNT{{S_COUNT{1'b1}}}}, + parameter M_CONNECT_WR = {M_COUNT{{S_COUNT{1'b1}}}}, + parameter M_ISSUE = {M_COUNT{32'd4}}, + parameter M_SECURE = {M_COUNT{1'b0}}, + parameter S_AW_REG_TYPE = {S_COUNT{2'd0}}, + parameter S_W_REG_TYPE = {S_COUNT{2'd0}}, + parameter S_B_REG_TYPE = {S_COUNT{2'd1}}, + parameter S_AR_REG_TYPE = {S_COUNT{2'd0}}, + parameter S_R_REG_TYPE = {S_COUNT{2'd2}}, + parameter M_AW_REG_TYPE = {M_COUNT{2'd1}}, + parameter M_W_REG_TYPE = {M_COUNT{2'd2}}, + parameter M_B_REG_TYPE = {M_COUNT{2'd0}}, + parameter M_AR_REG_TYPE = {M_COUNT{2'd1}}, + parameter M_R_REG_TYPE = {M_COUNT{2'd0}} + /* verilator lint_on WIDTHTRUNC */ +) +(); + +logic clk; +logic rst; + +taxi_axil_if #( + .DATA_W(DATA_W), + .ADDR_W(ADDR_W), + .STRB_W(STRB_W), + .AWUSER_EN(AWUSER_EN), + .AWUSER_W(AWUSER_W), + .WUSER_EN(WUSER_EN), + .WUSER_W(WUSER_W), + .BUSER_EN(BUSER_EN), + .BUSER_W(BUSER_W), + .ARUSER_EN(ARUSER_EN), + .ARUSER_W(ARUSER_W), + .RUSER_EN(RUSER_EN), + .RUSER_W(RUSER_W) +) s_axil[S_COUNT](); + +taxi_axil_if #( + .DATA_W(DATA_W), + .ADDR_W(ADDR_W), + .STRB_W(STRB_W), + .AWUSER_EN(AWUSER_EN), + .AWUSER_W(AWUSER_W), + .WUSER_EN(WUSER_EN), + .WUSER_W(WUSER_W), + .BUSER_EN(BUSER_EN), + .BUSER_W(BUSER_W), + .ARUSER_EN(ARUSER_EN), + .ARUSER_W(ARUSER_W), + .RUSER_EN(RUSER_EN), + .RUSER_W(RUSER_W) +) m_axil[M_COUNT](); + +taxi_axil_crossbar #( + .S_COUNT(S_COUNT), + .M_COUNT(M_COUNT), + .ADDR_W(ADDR_W), + .S_ACCEPT(S_ACCEPT), + .M_REGIONS(M_REGIONS), + .M_BASE_ADDR(M_BASE_ADDR), + .M_ADDR_W(M_ADDR_W), + .M_CONNECT_RD(M_CONNECT_RD), + .M_CONNECT_WR(M_CONNECT_WR), + .M_ISSUE(M_ISSUE), + .M_SECURE(M_SECURE), + .S_AW_REG_TYPE(S_AW_REG_TYPE), + .S_W_REG_TYPE(S_W_REG_TYPE), + .S_B_REG_TYPE(S_B_REG_TYPE), + .S_AR_REG_TYPE(S_AR_REG_TYPE), + .S_R_REG_TYPE(S_R_REG_TYPE), + .M_AW_REG_TYPE(M_AW_REG_TYPE), + .M_W_REG_TYPE(M_W_REG_TYPE), + .M_B_REG_TYPE(M_B_REG_TYPE), + .M_AR_REG_TYPE(M_AR_REG_TYPE), + .M_R_REG_TYPE(M_R_REG_TYPE) +) +uut ( + .clk(clk), + .rst(rst), + + /* + * AXI4-lite slave interface + */ + .s_axil_wr(s_axil), + .s_axil_rd(s_axil), + + /* + * AXI4-lite master interface + */ + .m_axil_wr(m_axil), + .m_axil_rd(m_axil) +); + +endmodule + +`resetall