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eth: Update example designs

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-10-02 16:11:07 -07:00
parent 76d4465081
commit 159c9d6241
45 changed files with 1561 additions and 1296 deletions
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16
src/eth/example/fb2CG/fpga/rtl/fpga.sv
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@@ -44,10 +44,10 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp_0_tx_p,
output wire logic [3:0] qsfp_0_tx_n,
input wire logic [3:0] qsfp_0_rx_p,
input wire logic [3:0] qsfp_0_rx_n,
output wire logic qsfp_0_tx_p[4],
output wire logic qsfp_0_tx_n[4],
input wire logic qsfp_0_rx_p[4],
input wire logic qsfp_0_rx_n[4],
input wire logic qsfp_0_mgt_refclk_p,
input wire logic qsfp_0_mgt_refclk_n,
input wire logic qsfp_0_mod_prsnt_n,
@@ -55,10 +55,10 @@ module fpga #
output wire logic qsfp_0_lp_mode,
input wire logic qsfp_0_intr_n,
output wire logic [3:0] qsfp_1_tx_p,
output wire logic [3:0] qsfp_1_tx_n,
input wire logic [3:0] qsfp_1_rx_p,
input wire logic [3:0] qsfp_1_rx_n,
output wire logic qsfp_1_tx_p[4],
output wire logic qsfp_1_tx_n[4],
input wire logic qsfp_1_rx_p[4],
input wire logic qsfp_1_rx_n[4],
input wire logic qsfp_1_mgt_refclk_p,
input wire logic qsfp_1_mgt_refclk_n,
input wire logic qsfp_1_mod_prsnt_n,