apb: Add APB interconnect module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
64
src/apb/tb/taxi_apb_interconnect/Makefile
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64
src/apb/tb/taxi_apb_interconnect/Makefile
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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#
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# Copyright (c) 2020-2025
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#
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# Authors:
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# - Alex Forencich
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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RTL_DIR = ../../rtl
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LIB_DIR = ../../lib
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TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
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DUT = taxi_apb_interconnect
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COCOTB_TEST_MODULES = test_$(DUT)
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COCOTB_TOPLEVEL = test_$(DUT)
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MODULE = $(COCOTB_TEST_MODULES)
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TOPLEVEL = $(COCOTB_TOPLEVEL)
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VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
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VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
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VERILOG_SOURCES += $(RTL_DIR)/taxi_apb_if.sv
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
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# module parameters
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export PARAM_M_CNT := 4
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export PARAM_DATA_W := 32
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export PARAM_ADDR_W := 32
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export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 )
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export PARAM_PAUSER_EN := 0
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export PARAM_PAUSER_W := 1
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export PARAM_PWUSER_EN := 0
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export PARAM_PWUSER_W := 1
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export PARAM_PBUSER_EN := 0
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export PARAM_PBUSER_W := 1
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export PARAM_PRUSER_EN := 0
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export PARAM_PRUSER_W := 1
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += -Wno-WIDTH
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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VERILATOR_TRACE = 1
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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259
src/apb/tb/taxi_apb_interconnect/test_taxi_apb_interconnect.py
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259
src/apb/tb/taxi_apb_interconnect/test_taxi_apb_interconnect.py
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#!/usr/bin/env python3
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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"""
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Copyright (c) 2020-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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"""
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import itertools
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import logging
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import os
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import random
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import cocotb
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import cocotb_test.simulator
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import pytest
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from cocotb.clock import Clock
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from cocotb.regression import TestFactory
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from cocotb.triggers import RisingEdge, Timer
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from cocotbext.axi import ApbBus, ApbMaster, ApbRam
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class TB(object):
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
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self.apb_master = ApbMaster(ApbBus.from_entity(dut.s_apb), dut.clk, dut.rst)
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self.apb_ram = [
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ApbRam(ApbBus.from_entity(ch), dut.clk, dut.rst, size=2**16)
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for ch in dut.m_apb
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]
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def set_idle_generator(self, generator=None):
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if generator:
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self.apb_master.set_pause_generator(generator())
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def set_backpressure_generator(self, generator=None):
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if generator:
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for ram in self.apb_ram:
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ram.set_pause_generator(generator())
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async def cycle_reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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async def run_test_write(
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dut, data_in=None, idle_inserter=None, backpressure_inserter=None, m=0
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):
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tb = TB(dut)
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byte_lanes = tb.apb_master.byte_lanes
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await tb.cycle_reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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for length in range(1, byte_lanes * 2):
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for offset in range(byte_lanes):
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tb.log.info("length %d, offset %d", length, offset)
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ram_addr = offset + 0x1000
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addr = ram_addr + m * 0x1000000
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test_data = bytearray([x % 256 for x in range(length)])
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tb.apb_ram[m].write(ram_addr - 128, b"\xaa" * (length + 256))
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await tb.apb_master.write(addr, test_data)
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tb.log.debug(
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"%s",
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tb.apb_ram[m].hexdump_str(
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(ram_addr & ~0xF) - 16,
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(((ram_addr & 0xF) + length - 1) & ~0xF) + 48,
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),
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)
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assert tb.apb_ram[m].read(ram_addr, length) == test_data
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assert tb.apb_ram[m].read(ram_addr - 1, 1) == b"\xaa"
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assert tb.apb_ram[m].read(ram_addr + length, 1) == b"\xaa"
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_test_read(
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dut, data_in=None, idle_inserter=None, backpressure_inserter=None, m=0
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):
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tb = TB(dut)
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byte_lanes = tb.apb_master.byte_lanes
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await tb.cycle_reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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for length in range(1, byte_lanes * 2):
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for offset in range(byte_lanes):
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tb.log.info("length %d, offset %d", length, offset)
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ram_addr = offset + 0x1000
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addr = ram_addr + m * 0x1000000
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test_data = bytearray([x % 256 for x in range(length)])
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tb.apb_ram[m].write(ram_addr, test_data)
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data = await tb.apb_master.read(addr, length)
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assert data.data == test_data
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
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tb = TB(dut)
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await tb.cycle_reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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async def worker(master, offset, aperture, count=16):
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for k in range(count):
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m = random.randrange(len(tb.apb_ram))
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length = random.randint(1, min(32, aperture))
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addr = offset + random.randint(0, aperture - length) + m * 0x1000000
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test_data = bytearray([x % 256 for x in range(length)])
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await Timer(random.randint(1, 100), "ns")
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await master.write(addr, test_data)
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await Timer(random.randint(1, 100), "ns")
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data = await master.read(addr, length)
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assert data.data == test_data
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workers = []
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for k in range(16):
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workers.append(
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cocotb.start_soon(
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worker(
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tb.apb_master,
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k * 0x1000,
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0x1000,
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count=16,
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)
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)
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)
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while workers:
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await workers.pop(0).join()
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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def cycle_pause():
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return itertools.cycle([1, 1, 1, 0])
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if getattr(cocotb, "top", None) is not None:
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m_cnt = len(cocotb.top.m_apb)
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for test in [run_test_write, run_test_read]:
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factory = TestFactory(test)
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factory.add_option("idle_inserter", [None, cycle_pause])
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factory.add_option("backpressure_inserter", [None, cycle_pause])
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factory.add_option("m", range(min(m_cnt, 2)))
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factory.generate_tests()
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factory = TestFactory(run_stress_test)
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factory.generate_tests()
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# cocotb-test
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tests_dir = os.path.abspath(os.path.dirname(__file__))
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rtl_dir = os.path.abspath(os.path.join(tests_dir, "..", "..", "rtl"))
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lib_dir = os.path.abspath(os.path.join(tests_dir, "..", "..", "lib"))
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taxi_src_dir = os.path.abspath(os.path.join(lib_dir, "taxi", "src"))
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def process_f_files(files):
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lst = {}
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for f in files:
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if f[-2:].lower() == ".f":
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with open(f, "r") as fp:
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l = fp.read().split()
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for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
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lst[os.path.basename(f)] = f
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else:
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lst[os.path.basename(f)] = f
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return list(lst.values())
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@pytest.mark.parametrize("data_w", [8, 16, 32])
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@pytest.mark.parametrize("m_cnt", [1, 4])
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def test_taxi_apb_interconnect(request, m_cnt, data_w):
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dut = "taxi_apb_interconnect"
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module = os.path.splitext(os.path.basename(__file__))[0]
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toplevel = module
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verilog_sources = [
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os.path.join(tests_dir, f"{toplevel}.sv"),
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os.path.join(rtl_dir, f"{dut}.sv"),
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os.path.join(rtl_dir, "taxi_apb_if.sv"),
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]
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verilog_sources = process_f_files(verilog_sources)
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parameters = {}
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parameters["M_CNT"] = m_cnt
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parameters["DATA_W"] = data_w
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parameters["ADDR_W"] = 32
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parameters["STRB_W"] = parameters["DATA_W"] // 8
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parameters["PAUSER_EN"] = 0
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parameters["PAUSER_W"] = 1
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parameters["PWUSER_EN"] = 0
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parameters["PWUSER_W"] = 1
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parameters["PRUSER_EN"] = 0
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parameters["PRUSER_W"] = 1
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parameters["PBUSER_EN"] = 0
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parameters["PBUSER_W"] = 1
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extra_env = {f"PARAM_{k}": str(v) for k, v in parameters.items()}
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sim_build = os.path.join(
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tests_dir, "sim_build", request.node.name.replace("[", "-").replace("]", "")
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)
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cocotb_test.simulator.run(
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simulator="verilator",
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python_search=[tests_dir],
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verilog_sources=verilog_sources,
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toplevel=toplevel,
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module=module,
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parameters=parameters,
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sim_build=sim_build,
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extra_env=extra_env,
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)
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@@ -0,0 +1,83 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* APB interconnect testbench
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*/
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module test_taxi_apb_interconnect #
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(
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/* verilator lint_off WIDTHTRUNC */
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parameter M_CNT = 4,
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parameter DATA_W = 32,
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parameter ADDR_W = 32,
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parameter STRB_W = (DATA_W/8),
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parameter logic PAUSER_EN = 1'b0,
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parameter PAUSER_W = 1,
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parameter logic PWUSER_EN = 1'b0,
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parameter PWUSER_W = 1,
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parameter logic PRUSER_EN = 1'b0,
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parameter PRUSER_W = 1,
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parameter logic PBUSER_EN = 1'b0,
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parameter PBUSER_W = 1,
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parameter M_REGIONS = 1,
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parameter M_BASE_ADDR = '0,
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parameter M_ADDR_W = {M_CNT{{M_REGIONS{32'd24}}}},
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parameter M_SECURE = {M_CNT{1'b0}}
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/* verilator lint_on WIDTHTRUNC */
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)
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();
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logic clk;
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logic rst;
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taxi_apb_if #(
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.DATA_W(DATA_W),
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.ADDR_W(ADDR_W),
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.STRB_W(STRB_W),
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.PAUSER_EN(PAUSER_EN),
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.PAUSER_W(PAUSER_W),
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.PWUSER_EN(PWUSER_EN),
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.PWUSER_W(PWUSER_W),
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.PRUSER_EN(PRUSER_EN),
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.PRUSER_W(PRUSER_W),
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.PBUSER_EN(PBUSER_EN),
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.PBUSER_W(PBUSER_W)
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) s_apb(), m_apb[M_CNT]();
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taxi_apb_interconnect #(
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.M_CNT(M_CNT),
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.ADDR_W(ADDR_W),
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.M_REGIONS(M_REGIONS),
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.M_BASE_ADDR(M_BASE_ADDR),
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.M_ADDR_W(M_ADDR_W),
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.M_SECURE(M_SECURE)
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)
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uut (
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.clk(clk),
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.rst(rst),
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/*
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* APB slave interface
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*/
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.s_apb(s_apb),
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/*
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* APB master interface
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*/
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.m_apb(m_apb)
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);
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endmodule
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`resetall
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