axi: Add AXI lite interconnect module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
502
src/axi/rtl/taxi_axil_interconnect_wr.sv
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502
src/axi/rtl/taxi_axil_interconnect_wr.sv
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@@ -0,0 +1,502 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2018-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 lite interconnect (write)
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*/
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module taxi_axil_interconnect_wr #
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(
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// Number of AXI inputs (slave interfaces)
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parameter S_COUNT = 4,
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// Number of AXI outputs (master interfaces)
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parameter M_COUNT = 4,
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// Address width in bits for address decoding
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parameter ADDR_W = 32,
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// Number of regions per master interface
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parameter M_REGIONS = 1,
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// TODO fix parametrization once verilator issue 5890 is fixed
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// Master interface base addresses
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// M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
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// set to zero for default addressing based on M_ADDR_W
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parameter M_BASE_ADDR = '0,
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// Master interface address widths
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// M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
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parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
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// Write connections between interfaces
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// M_COUNT concatenated fields of S_COUNT bits
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parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
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// Secure master (fail operations based on awprot/arprot)
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// M_COUNT bits
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parameter M_SECURE = {M_COUNT{1'b0}}
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI4-lite slave interfaces
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*/
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taxi_axil_if.wr_slv s_axil_wr[S_COUNT],
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/*
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* AXI4-lite master interfaces
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*/
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taxi_axil_if.wr_mst m_axil_wr[M_COUNT]
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);
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// extract parameters
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localparam DATA_W = s_axil_wr.DATA_W;
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localparam S_ADDR_W = s_axil_wr.ADDR_W;
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localparam STRB_W = s_axil_wr.STRB_W;
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localparam logic AWUSER_EN = s_axil_wr.AWUSER_EN && m_axil_wr.AWUSER_EN;
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localparam AWUSER_W = s_axil_wr.AWUSER_W;
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localparam logic WUSER_EN = s_axil_wr.WUSER_EN && m_axil_wr.WUSER_EN;
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localparam WUSER_W = s_axil_wr.WUSER_W;
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localparam logic BUSER_EN = s_axil_wr.BUSER_EN && m_axil_wr.BUSER_EN;
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localparam BUSER_W = s_axil_wr.BUSER_W;
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localparam CL_S_COUNT = $clog2(S_COUNT);
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localparam CL_M_COUNT = $clog2(M_COUNT);
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localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
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localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
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localparam [M_COUNT*M_REGIONS-1:0][31:0] M_ADDR_W_INT = M_ADDR_W;
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localparam [M_COUNT-1:0][S_COUNT-1:0] M_CONNECT_INT = M_CONNECT;
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localparam [M_COUNT-1:0] M_SECURE_INT = M_SECURE;
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// default address computation
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function [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] calcBaseAddrs(input [31:0] dummy);
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logic [ADDR_W-1:0] base;
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logic [ADDR_W-1:0] width;
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logic [ADDR_W-1:0] size;
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logic [ADDR_W-1:0] mask;
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begin
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calcBaseAddrs = '0;
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base = 0;
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for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
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width = M_ADDR_W_INT[i];
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mask = {ADDR_W{1'b1}} >> (ADDR_W - width);
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size = mask + 1;
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if (width > 0) begin
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if ((base & mask) != 0) begin
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base = base + size - (base & mask); // align
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end
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calcBaseAddrs[i] = base;
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base = base + size; // increment
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end
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end
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end
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endfunction
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localparam [M_COUNT*M_REGIONS-1:0][ADDR_W-1:0] M_BASE_ADDR_INT = M_BASE_ADDR != 0 ? (M_COUNT*M_REGIONS*ADDR_W)'(M_BASE_ADDR) : calcBaseAddrs(0);
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// check configuration
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if (s_axil_wr.ADDR_W != ADDR_W)
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$fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)");
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if (m_axil_wr.DATA_W != DATA_W)
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$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
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if (m_axil_wr.STRB_W != STRB_W)
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$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
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initial begin
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for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
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/* verilator lint_off UNSIGNED */
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if (M_ADDR_W_INT[i] != 0 && (M_ADDR_W_INT[i] < $clog2(STRB_W) || M_ADDR_W_INT[i] > ADDR_W)) begin
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$error("Error: address width out of range (instance %m)");
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$finish;
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end
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/* verilator lint_on UNSIGNED */
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end
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$display("Addressing configuration for axil_interconnect instance %m");
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for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
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if (M_ADDR_W_INT[i] != 0) begin
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$display("%2d (%2d): %x / %02d -- %x-%x",
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i/M_REGIONS, i%M_REGIONS,
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M_BASE_ADDR_INT[i],
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M_ADDR_W_INT[i],
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M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
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M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
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);
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end
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end
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for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
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if ((M_BASE_ADDR_INT[i] & (2**M_ADDR_W_INT[i]-1)) != 0) begin
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$display("Region not aligned:");
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$display("%2d (%2d): %x / %2d -- %x-%x",
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i/M_REGIONS, i%M_REGIONS,
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M_BASE_ADDR_INT[i],
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M_ADDR_W_INT[i],
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M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
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M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
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);
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$error("Error: address range not aligned (instance %m)");
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$finish;
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end
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end
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for (integer i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
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for (integer j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin
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if (M_ADDR_W_INT[i] != 0 && M_ADDR_W_INT[j] != 0) begin
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if (((M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i])) <= (M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))))
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&& ((M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j])) <= (M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))))) begin
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$display("Overlapping regions:");
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$display("%2d (%2d): %x / %2d -- %x-%x",
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i/M_REGIONS, i%M_REGIONS,
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M_BASE_ADDR_INT[i],
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M_ADDR_W_INT[i],
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M_BASE_ADDR_INT[i] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[i]),
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M_BASE_ADDR_INT[i] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[i]))
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);
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$display("%2d (%2d): %x / %2d -- %x-%x",
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j/M_REGIONS, j%M_REGIONS,
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M_BASE_ADDR_INT[j],
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M_ADDR_W_INT[j],
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M_BASE_ADDR_INT[j] & ({ADDR_W{1'b1}} << M_ADDR_W_INT[j]),
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M_BASE_ADDR_INT[j] | ({ADDR_W{1'b1}} >> (ADDR_W - M_ADDR_W_INT[j]))
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);
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$error("Error: address ranges overlap (instance %m)");
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$finish;
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end
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end
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end
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end
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end
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localparam logic [2:0]
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STATE_IDLE = 3'd0,
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STATE_DECODE = 3'd1,
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STATE_WRITE = 3'd2,
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STATE_WRITE_RESP = 3'd3,
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STATE_WRITE_DROP = 3'd4,
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STATE_WAIT_IDLE = 3'd5;
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logic [2:0] state_reg = STATE_IDLE, state_next;
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logic match;
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logic [CL_M_COUNT_INT-1:0] m_select_reg = '0, m_select_next;
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logic [ADDR_W-1:0] axil_awaddr_reg = '0, axil_awaddr_next;
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logic axil_awaddr_valid_reg = 1'b0, axil_awaddr_valid_next;
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logic [2:0] axil_awprot_reg = 3'b000, axil_awprot_next;
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logic [AWUSER_W-1:0] axil_awuser_reg = '0, axil_awuser_next;
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logic [DATA_W-1:0] axil_wdata_reg = '0, axil_wdata_next;
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logic [STRB_W-1:0] axil_wstrb_reg = '0, axil_wstrb_next;
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logic [WUSER_W-1:0] axil_wuser_reg = '0, axil_wuser_next;
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logic [1:0] axil_bresp_reg = 2'b00, axil_bresp_next;
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logic [BUSER_W-1:0] axil_buser_reg = '0, axil_buser_next;
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logic [S_COUNT-1:0] s_axil_awready_reg = '0, s_axil_awready_next;
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logic [S_COUNT-1:0] s_axil_wready_reg = '0, s_axil_wready_next;
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logic [S_COUNT-1:0] s_axil_bvalid_reg = '0, s_axil_bvalid_next;
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logic [M_COUNT-1:0] m_axil_awvalid_reg = '0, m_axil_awvalid_next;
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logic [M_COUNT-1:0] m_axil_wvalid_reg = '0, m_axil_wvalid_next;
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logic [M_COUNT-1:0] m_axil_bready_reg = '0, m_axil_bready_next;
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// unpack interface array
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wire [ADDR_W-1:0] s_axil_awaddr[S_COUNT];
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wire [2:0] s_axil_awprot[S_COUNT];
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wire [AWUSER_W-1:0] s_axil_awuser[S_COUNT];
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wire [S_COUNT-1:0] s_axil_awvalid;
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wire [DATA_W-1:0] s_axil_wdata[S_COUNT];
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wire [STRB_W-1:0] s_axil_wstrb[S_COUNT];
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wire [WUSER_W-1:0] s_axil_wuser[S_COUNT];
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wire [S_COUNT-1:0] s_axil_wvalid;
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wire [S_COUNT-1:0] s_axil_bready;
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wire [M_COUNT-1:0] m_axil_awready;
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wire [M_COUNT-1:0] m_axil_wready;
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wire [1:0] m_axil_bresp[M_COUNT];
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wire [BUSER_W-1:0] m_axil_buser[M_COUNT];
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wire [M_COUNT-1:0] m_axil_bvalid;
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for (genvar n = 0; n < S_COUNT; n = n + 1) begin
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assign s_axil_awaddr[n] = s_axil_wr[n].awaddr;
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assign s_axil_awprot[n] = s_axil_wr[n].awprot;
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assign s_axil_awuser[n] = s_axil_wr[n].awuser;
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assign s_axil_awvalid[n] = s_axil_wr[n].awvalid;
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assign s_axil_wr[n].awready = s_axil_awready_reg[n];
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assign s_axil_wdata[n] = s_axil_wr[n].wdata;
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assign s_axil_wstrb[n] = s_axil_wr[n].wstrb;
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assign s_axil_wuser[n] = s_axil_wr[n].wuser;
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assign s_axil_wvalid[n] = s_axil_wr[n].wvalid;
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assign s_axil_wr[n].wready = s_axil_wready_reg[n];
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assign s_axil_wr[n].bresp = axil_bresp_reg;
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assign s_axil_wr[n].buser = BUSER_EN ? axil_buser_reg : '0;
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assign s_axil_wr[n].bvalid = s_axil_bvalid_reg[n];
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assign s_axil_bready[n] = s_axil_wr[n].bready;
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end
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for (genvar n = 0; n < M_COUNT; n = n + 1) begin
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assign m_axil_wr[n].awaddr = axil_awaddr_reg;
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assign m_axil_wr[n].awprot = axil_awprot_reg;
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assign m_axil_wr[n].awuser = AWUSER_EN ? axil_awuser_reg : '0;
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assign m_axil_wr[n].awvalid = m_axil_awvalid_reg[n];
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assign m_axil_awready[n] = m_axil_wr[n].awready;
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assign m_axil_wr[n].wdata = axil_wdata_reg;
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assign m_axil_wr[n].wstrb = axil_wstrb_reg;
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assign m_axil_wr[n].wuser = AWUSER_EN ? axil_wuser_reg : '0;
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assign m_axil_wr[n].wvalid = m_axil_wvalid_reg[n];
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assign m_axil_wready[n] = m_axil_wr[n].wready;
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assign m_axil_bresp[n] = m_axil_wr[n].bresp;
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assign m_axil_buser[n] = m_axil_wr[n].buser;
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assign m_axil_bvalid[n] = m_axil_wr[n].bvalid;
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assign m_axil_wr[n].bready = m_axil_bready_reg[n];
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end
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// slave side mux
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wire [CL_S_COUNT_INT-1:0] s_select;
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wire [ADDR_W-1:0] current_s_axil_awaddr = s_axil_awaddr[s_select];
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wire [2:0] current_s_axil_awprot = s_axil_awprot[s_select];
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wire [AWUSER_W-1:0] current_s_axil_awuser = s_axil_awuser[s_select];
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wire current_s_axil_awvalid = s_axil_awvalid[s_select];
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wire [DATA_W-1:0] current_s_axil_wdata = s_axil_wdata[s_select];
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wire [STRB_W-1:0] current_s_axil_wstrb = s_axil_wstrb[s_select];
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wire [WUSER_W-1:0] current_s_axil_wuser = s_axil_wuser[s_select];
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wire current_s_axil_wvalid = s_axil_wvalid[s_select];
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wire current_s_axil_bready = s_axil_bready[s_select];
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// master side mux
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wire current_m_axil_awready = m_axil_awready[m_select_reg];
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wire current_m_axil_wready = m_axil_wready[m_select_reg];
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wire [1:0] current_m_axil_bresp = m_axil_bresp[m_select_reg];
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wire [BUSER_W-1:0] current_m_axil_buser = m_axil_buser[m_select_reg];
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wire current_m_axil_bvalid = m_axil_bvalid[m_select_reg];
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// arbiter instance
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wire [S_COUNT-1:0] req;
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wire [S_COUNT-1:0] ack;
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wire [S_COUNT-1:0] grant;
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wire grant_valid;
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wire [CL_S_COUNT_INT-1:0] grant_index;
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assign s_select = grant_index;
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if (S_COUNT > 1) begin : arb
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taxi_arbiter #(
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.PORTS(S_COUNT),
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.ARB_ROUND_ROBIN(1),
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.ARB_BLOCK(1),
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.ARB_BLOCK_ACK(1),
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.LSB_HIGH_PRIO(1)
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)
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arb_inst (
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.clk(clk),
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.rst(rst),
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.req(req),
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.ack(ack),
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.grant(grant),
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.grant_valid(grant_valid),
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.grant_index(grant_index)
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);
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end else begin
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logic grant_valid_reg = 1'b0;
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always @(posedge clk) begin
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if (req) begin
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grant_valid_reg <= 1'b1;
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end
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if (ack || rst) begin
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grant_valid_reg <= 1'b0;
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end
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end
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assign grant_valid = grant_valid_reg;
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assign grant = '1;
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assign grant_index = '0;
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end
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assign req = s_axil_awvalid;
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assign ack = grant & s_axil_bvalid_reg & s_axil_bready;
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always_comb begin
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state_next = STATE_IDLE;
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match = 1'b0;
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m_select_next = m_select_reg;
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axil_awaddr_next = axil_awaddr_reg;
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axil_awaddr_valid_next = axil_awaddr_valid_reg;
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axil_awprot_next = axil_awprot_reg;
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axil_awuser_next = axil_awuser_reg;
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axil_wdata_next = axil_wdata_reg;
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axil_wstrb_next = axil_wstrb_reg;
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axil_wuser_next = axil_wuser_reg;
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axil_bresp_next = axil_bresp_reg;
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axil_buser_next = axil_buser_reg;
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s_axil_awready_next = '0;
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s_axil_wready_next = '0;
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s_axil_bvalid_next = s_axil_bvalid_reg & ~s_axil_bready;
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m_axil_awvalid_next = m_axil_awvalid_reg & ~m_axil_awready;
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m_axil_wvalid_next = m_axil_wvalid_reg & ~m_axil_wready;
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m_axil_bready_next = '0;
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case (state_reg)
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STATE_IDLE: begin
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// idle state; wait for arbitration
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axil_awaddr_valid_next = 1'b1;
|
||||
axil_awaddr_next = current_s_axil_awaddr;
|
||||
axil_awprot_next = current_s_axil_awprot;
|
||||
axil_awuser_next = current_s_axil_awuser;
|
||||
|
||||
if (grant_valid) begin
|
||||
s_axil_awready_next[grant_index] = 1'b1;
|
||||
state_next = STATE_DECODE;
|
||||
end else begin
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end
|
||||
STATE_DECODE: begin
|
||||
// decode state; determine master interface
|
||||
|
||||
match = 1'b0;
|
||||
for (integer i = 0; i < M_COUNT; i = i + 1) begin
|
||||
for (integer j = 0; j < M_REGIONS; j = j + 1) begin
|
||||
if (M_ADDR_W_INT[i*M_REGIONS+j] != 0 && (!M_SECURE_INT[i] || !axil_awprot_reg[1]) && M_CONNECT_INT[i][s_select] && (axil_awaddr_reg >> M_ADDR_W_INT[i*M_REGIONS+j]) == (M_BASE_ADDR_INT[i*M_REGIONS+j] >> M_ADDR_W_INT[i*M_REGIONS+j])) begin
|
||||
m_select_next = CL_M_COUNT_INT'(i);
|
||||
match = 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
s_axil_wready_next[s_select] = 1'b1;
|
||||
|
||||
if (match) begin
|
||||
state_next = STATE_WRITE;
|
||||
end else begin
|
||||
// no match; return decode error
|
||||
state_next = STATE_WRITE_DROP;
|
||||
end
|
||||
end
|
||||
STATE_WRITE: begin
|
||||
// write state; store and forward write data
|
||||
s_axil_wready_next[s_select] = 1'b1;
|
||||
|
||||
if (axil_awaddr_valid_reg) begin
|
||||
m_axil_awvalid_next[m_select_reg] = 1'b1;
|
||||
end
|
||||
axil_awaddr_valid_next = 1'b0;
|
||||
|
||||
axil_wdata_next = current_s_axil_wdata;
|
||||
axil_wstrb_next = current_s_axil_wstrb;
|
||||
axil_wuser_next = current_s_axil_wuser;
|
||||
|
||||
if (s_axil_wready_reg != 0 && current_s_axil_wvalid) begin
|
||||
s_axil_wready_next[s_select] = 1'b0;
|
||||
m_axil_wvalid_next[m_select_reg] = 1'b1;
|
||||
m_axil_bready_next[m_select_reg] = 1'b1;
|
||||
state_next = STATE_WRITE_RESP;
|
||||
end else begin
|
||||
state_next = STATE_WRITE;
|
||||
end
|
||||
end
|
||||
STATE_WRITE_RESP: begin
|
||||
// write response state; store and forward write response
|
||||
m_axil_bready_next[m_select_reg] = 1'b1;
|
||||
|
||||
axil_bresp_next = current_m_axil_bresp;
|
||||
axil_buser_next = current_m_axil_buser;
|
||||
|
||||
if (m_axil_bready_reg != 0 && current_m_axil_bvalid) begin
|
||||
m_axil_bready_next[m_select_reg] = 1'b0;
|
||||
s_axil_bvalid_next[s_select] = 1'b1;
|
||||
state_next = STATE_WAIT_IDLE;
|
||||
end else begin
|
||||
state_next = STATE_WRITE_RESP;
|
||||
end
|
||||
end
|
||||
STATE_WRITE_DROP: begin
|
||||
// write drop state; drop write data
|
||||
s_axil_wready_next[s_select] = 1'b1;
|
||||
|
||||
axil_awaddr_valid_next = 1'b0;
|
||||
|
||||
axil_bresp_next = 2'b11;
|
||||
axil_buser_next = '0;
|
||||
|
||||
if (s_axil_wready_reg != 0 && current_s_axil_wvalid) begin
|
||||
s_axil_wready_next[s_select] = 1'b0;
|
||||
s_axil_bvalid_next[s_select] = 1'b1;
|
||||
state_next = STATE_WAIT_IDLE;
|
||||
end else begin
|
||||
state_next = STATE_WRITE_DROP;
|
||||
end
|
||||
end
|
||||
STATE_WAIT_IDLE: begin
|
||||
// wait for idle state; wait until grant valid is deasserted
|
||||
|
||||
if (grant_valid == 0 || ack != 0) begin
|
||||
state_next = STATE_IDLE;
|
||||
end else begin
|
||||
state_next = STATE_WAIT_IDLE;
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
// invalid state
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
state_reg <= state_next;
|
||||
|
||||
m_select_reg <= m_select_next;
|
||||
|
||||
axil_awaddr_reg <= axil_awaddr_next;
|
||||
axil_awaddr_valid_reg <= axil_awaddr_valid_next;
|
||||
axil_awprot_reg <= axil_awprot_next;
|
||||
axil_awuser_reg <= axil_awuser_next;
|
||||
axil_wdata_reg <= axil_wdata_next;
|
||||
axil_wstrb_reg <= axil_wstrb_next;
|
||||
axil_wuser_reg <= axil_wuser_next;
|
||||
axil_bresp_reg <= axil_bresp_next;
|
||||
axil_buser_reg <= axil_buser_next;
|
||||
|
||||
s_axil_awready_reg <= s_axil_awready_next;
|
||||
s_axil_wready_reg <= s_axil_wready_next;
|
||||
s_axil_bvalid_reg <= s_axil_bvalid_next;
|
||||
|
||||
m_axil_awvalid_reg <= m_axil_awvalid_next;
|
||||
m_axil_wvalid_reg <= m_axil_wvalid_next;
|
||||
m_axil_bready_reg <= m_axil_bready_next;
|
||||
|
||||
if (rst) begin
|
||||
state_reg <= STATE_IDLE;
|
||||
|
||||
s_axil_awready_reg <= '0;
|
||||
s_axil_wready_reg <= '0;
|
||||
s_axil_bvalid_reg <= '0;
|
||||
|
||||
m_axil_awvalid_reg <= '0;
|
||||
m_axil_wvalid_reg <= '0;
|
||||
m_axil_bready_reg <= '0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user