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eth: Rename gearbox start signals to sync

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-06-12 15:45:07 -07:00
parent ca3ee2d197
commit 4e66dd0f98
33 changed files with 137 additions and 137 deletions
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2
src/eth/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py
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@@ -75,7 +75,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py
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@@ -78,7 +78,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -98,7 +98,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/KR260/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -89,7 +89,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/Nexus_K3P_Q/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -75,7 +75,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/Nexus_K3P_S/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -74,7 +74,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -85,7 +85,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -86,7 +86,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/XUPP3R/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -82,7 +82,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -104,7 +104,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -92,7 +92,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/ZCU111/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -76,7 +76,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg

2
src/eth/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -76,7 +76,7 @@ class TB:
data_valid=gt_inst.serdes_tx_data_valid,
hdr=gt_inst.serdes_tx_hdr,
hdr_valid=gt_inst.serdes_tx_hdr_valid,
gbx_start=gt_inst.serdes_tx_gbx_start,
gbx_sync=gt_inst.serdes_tx_gbx_sync,
clock=gt_inst.tx_clk,
reverse=True,
gbx_cfg=gbx_cfg