From 5f814e7da8db166115a770430a07b2c312a4f245 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 7 Nov 2025 01:51:18 -0800 Subject: [PATCH] Clean up always blocks Signed-off-by: Alex Forencich --- src/axi/rtl/taxi_axil_apb_adapter.sv | 4 ++-- src/axis/rtl/taxi_axis_broadcast.sv | 4 ++-- src/axis/rtl/taxi_axis_cobs_encode.sv | 10 +++++----- src/dma/rtl/taxi_dma_client_axis_sink.sv | 4 ++-- src/eth/rtl/taxi_eth_mac_1g_gmii_fifo.sv | 2 +- src/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.sv | 2 +- src/eth/rtl/taxi_eth_mac_phy_10g_fifo.sv | 8 ++++---- src/eth/rtl/taxi_eth_phy_10g_rx_if.sv | 2 +- src/eth/rtl/taxi_eth_phy_10g_tx_if.sv | 2 +- src/eth/rtl/taxi_xgmii_baser_dec.sv | 2 +- src/eth/rtl/taxi_xgmii_baser_enc.sv | 2 +- src/eth/rtl/us/taxi_eth_phy_10g_us_gt_ll.sv | 4 ++-- src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.sv | 8 ++++---- src/io/rtl/taxi_led_sreg.sv | 2 +- src/lfsr/rtl/taxi_lfsr_prbs_gen.sv | 2 +- src/zircon/rtl/zircon_ip_rx_parse.sv | 2 +- 16 files changed, 30 insertions(+), 30 deletions(-) diff --git a/src/axi/rtl/taxi_axil_apb_adapter.sv b/src/axi/rtl/taxi_axil_apb_adapter.sv index fd76ca8..e37df19 100644 --- a/src/axi/rtl/taxi_axil_apb_adapter.sv +++ b/src/axi/rtl/taxi_axil_apb_adapter.sv @@ -248,7 +248,7 @@ if (APB_BYTE_LANES == AXIL_BYTE_LANES) begin : translate endcase end - always @(posedge clk) begin + always_ff @(posedge clk) begin state_reg <= state_next; last_read_reg <= last_read_next; @@ -447,7 +447,7 @@ end else if (APB_BYTE_LANES > AXIL_BYTE_LANES) begin : upsize endcase end - always @(posedge clk) begin + always_ff @(posedge clk) begin state_reg <= state_next; last_read_reg <= last_read_next; diff --git a/src/axis/rtl/taxi_axis_broadcast.sv b/src/axis/rtl/taxi_axis_broadcast.sv index c1babc7..c26ab05 100644 --- a/src/axis/rtl/taxi_axis_broadcast.sv +++ b/src/axis/rtl/taxi_axis_broadcast.sv @@ -105,7 +105,7 @@ end // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) wire s_axis_tready_early = ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || (!temp_m_axis_tvalid_reg && (m_axis_tvalid == 0 || !s_axis.tvalid)); -always @* begin +always_comb begin // transfer sink ready state to source m_axis_tvalid_next = m_axis_tvalid_reg & ~m_axis_tready; temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg; @@ -133,7 +133,7 @@ always @* begin end end -always @(posedge clk) begin +always_ff @(posedge clk) begin s_axis_tready_reg <= s_axis_tready_early; m_axis_tvalid_reg <= m_axis_tvalid_next; temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next; diff --git a/src/axis/rtl/taxi_axis_cobs_encode.sv b/src/axis/rtl/taxi_axis_cobs_encode.sv index f601f2a..c5895ff 100644 --- a/src/axis/rtl/taxi_axis_cobs_encode.sv +++ b/src/axis/rtl/taxi_axis_cobs_encode.sv @@ -141,7 +141,7 @@ data_fifo_inst ( .status_good_frame() ); -always @* begin +always_comb begin input_state_next = INPUT_STATE_IDLE; input_count_next = input_count_reg; @@ -304,7 +304,7 @@ always @* begin endcase end -always @* begin +always_comb begin output_state_next = OUTPUT_STATE_IDLE; output_count_next = output_count_reg; @@ -365,7 +365,7 @@ always @* begin endcase end -always @(posedge clk) begin +always_ff @(posedge clk) begin input_state_reg <= input_state_next; output_state_reg <= output_state_next; @@ -407,7 +407,7 @@ assign m_axis.tuser = m_axis_tuser_reg; // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) assign m_axis_tready_int_early = m_axis.tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int)); -always @* begin +always_comb begin // transfer sink ready state to source m_axis_tvalid_next = m_axis_tvalid_reg; temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg; @@ -435,7 +435,7 @@ always @* begin end end -always @(posedge clk) begin +always_ff @(posedge clk) begin m_axis_tvalid_reg <= m_axis_tvalid_next; m_axis_tready_int_reg <= m_axis_tready_int_early; temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next; diff --git a/src/dma/rtl/taxi_dma_client_axis_sink.sv b/src/dma/rtl/taxi_dma_client_axis_sink.sv index 625cf9c..55f5f66 100644 --- a/src/dma/rtl/taxi_dma_client_axis_sink.sv +++ b/src/dma/rtl/taxi_dma_client_axis_sink.sv @@ -418,7 +418,7 @@ always_comb begin end end -always @(posedge clk) begin +always_ff @(posedge clk) begin state_reg <= state_next; desc_req_ready_reg <= desc_req_ready_next; @@ -515,7 +515,7 @@ for (genvar n = 0; n < RAM_SEGS; n = n + 1) begin assign out_done[n] = done_reg; - always @(posedge clk) begin + always_ff @(posedge clk) begin ram_wr_cmd_valid_reg <= ram_wr_cmd_valid_reg && !dma_ram_wr.wr_cmd_ready[n]; out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_AW-1); diff --git a/src/eth/rtl/taxi_eth_mac_1g_gmii_fifo.sv b/src/eth/rtl/taxi_eth_mac_1g_gmii_fifo.sv index f5be693..383c273 100644 --- a/src/eth/rtl/taxi_eth_mac_1g_gmii_fifo.sv +++ b/src/eth/rtl/taxi_eth_mac_1g_gmii_fifo.sv @@ -188,7 +188,7 @@ reg [1:0] link_speed_sync_reg_2 = 2'b10; assign link_speed = link_speed_sync_reg_2; -always @(posedge logic_clk) begin +always_ff @(posedge logic_clk) begin link_speed_sync_reg_1 <= link_speed_int; link_speed_sync_reg_2 <= link_speed_sync_reg_1; end diff --git a/src/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.sv b/src/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.sv index f4deb8b..acfc832 100644 --- a/src/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.sv +++ b/src/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.sv @@ -187,7 +187,7 @@ reg [1:0] link_speed_sync_reg_2 = 2'b10; assign link_speed = link_speed_sync_reg_2; -always @(posedge logic_clk) begin +always_ff @(posedge logic_clk) begin link_speed_sync_reg_1 <= link_speed_int; link_speed_sync_reg_2 <= link_speed_sync_reg_1; end diff --git a/src/eth/rtl/taxi_eth_mac_phy_10g_fifo.sv b/src/eth/rtl/taxi_eth_mac_phy_10g_fifo.sv index 930126e..9a57184 100644 --- a/src/eth/rtl/taxi_eth_mac_phy_10g_fifo.sv +++ b/src/eth/rtl/taxi_eth_mac_phy_10g_fifo.sv @@ -161,7 +161,7 @@ reg [0:0] tx_sync_reg_4 = '0; assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0]; -always @(posedge tx_clk or posedge tx_rst) begin +always_ff @(posedge tx_clk or posedge tx_rst) begin if (tx_rst) begin tx_sync_reg_1 <= '0; end else begin @@ -169,7 +169,7 @@ always @(posedge tx_clk or posedge tx_rst) begin end end -always @(posedge logic_clk or posedge logic_rst) begin +always_ff @(posedge logic_clk or posedge logic_rst) begin if (logic_rst) begin tx_sync_reg_2 <= '0; tx_sync_reg_3 <= '0; @@ -202,7 +202,7 @@ assign rx_block_lock = rx_sync_reg_4[4]; assign rx_high_ber = rx_sync_reg_4[5]; assign rx_status = rx_sync_reg_4[6]; -always @(posedge rx_clk or posedge rx_rst) begin +always_ff @(posedge rx_clk or posedge rx_rst) begin if (rx_rst) begin rx_sync_reg_1 <= '0; end else begin @@ -216,7 +216,7 @@ always @(posedge rx_clk or posedge rx_rst) begin end end -always @(posedge logic_clk or posedge logic_rst) begin +always_ff @(posedge logic_clk or posedge logic_rst) begin if (logic_rst) begin rx_sync_reg_2 <= '0; rx_sync_reg_3 <= '0; diff --git a/src/eth/rtl/taxi_eth_phy_10g_rx_if.sv b/src/eth/rtl/taxi_eth_phy_10g_rx_if.sv index 21b3cbd..66527ef 100644 --- a/src/eth/rtl/taxi_eth_phy_10g_rx_if.sv +++ b/src/eth/rtl/taxi_eth_phy_10g_rx_if.sv @@ -111,7 +111,7 @@ if (SERDES_PIPELINE > 0) begin serdes_rx_hdr_valid_pipe_reg[n] = '0; end - always @(posedge clk) begin + always_ff @(posedge clk) begin serdes_rx_data_pipe_reg[n] <= n == 0 ? serdes_rx_data_rev : serdes_rx_data_pipe_reg[n-1]; serdes_rx_data_valid_pipe_reg[n] <= n == 0 ? serdes_rx_data_valid : serdes_rx_data_valid_pipe_reg[n-1]; serdes_rx_hdr_pipe_reg[n] <= n == 0 ? serdes_rx_hdr_rev : serdes_rx_hdr_pipe_reg[n-1]; diff --git a/src/eth/rtl/taxi_eth_phy_10g_tx_if.sv b/src/eth/rtl/taxi_eth_phy_10g_tx_if.sv index 2ca7617..d6aa181 100644 --- a/src/eth/rtl/taxi_eth_phy_10g_tx_if.sv +++ b/src/eth/rtl/taxi_eth_phy_10g_tx_if.sv @@ -119,7 +119,7 @@ if (SERDES_PIPELINE > 0) begin serdes_tx_gbx_sync_pipe_reg[n] = '0; end - always @(posedge clk) begin + always_ff @(posedge clk) begin serdes_tx_data_pipe_reg[n] <= n == 0 ? serdes_tx_data_int : serdes_tx_data_pipe_reg[n-1]; serdes_tx_data_valid_pipe_reg[n] <= n == 0 ? serdes_tx_data_valid_reg : serdes_tx_data_valid_pipe_reg[n-1]; serdes_tx_hdr_pipe_reg[n] <= n == 0 ? serdes_tx_hdr_int : serdes_tx_hdr_pipe_reg[n-1]; diff --git a/src/eth/rtl/taxi_xgmii_baser_dec.sv b/src/eth/rtl/taxi_xgmii_baser_dec.sv index 8fccb90..ca0884f 100644 --- a/src/eth/rtl/taxi_xgmii_baser_dec.sv +++ b/src/eth/rtl/taxi_xgmii_baser_dec.sv @@ -152,7 +152,7 @@ end else begin : repack_in assign encoded_rx_data_valid_int = encoded_rx_data_valid_reg && (GBX_IF_EN ? encoded_rx_data_valid : 1'b1); assign encoded_rx_hdr_int = encoded_rx_hdr_reg; - always @(posedge clk) begin + always_ff @(posedge clk) begin if (!GBX_IF_EN || encoded_rx_data_valid) begin encoded_rx_data_reg <= encoded_rx_data; encoded_rx_data_valid_reg <= encoded_rx_hdr_valid; diff --git a/src/eth/rtl/taxi_xgmii_baser_enc.sv b/src/eth/rtl/taxi_xgmii_baser_enc.sv index 6b82301..a781903 100644 --- a/src/eth/rtl/taxi_xgmii_baser_enc.sv +++ b/src/eth/rtl/taxi_xgmii_baser_enc.sv @@ -157,7 +157,7 @@ end else begin : repack_in assign xgmii_txc_int = {xgmii_txc, xgmii_txc_reg}; assign xgmii_tx_valid_int = xgmii_tx_valid_reg && (GBX_IF_EN ? xgmii_tx_valid : 1'b1); - always @(posedge clk) begin + always_ff @(posedge clk) begin if (!GBX_IF_EN || xgmii_tx_valid) begin xgmii_txd_reg <= xgmii_txd; xgmii_txc_reg <= xgmii_txc; diff --git a/src/eth/rtl/us/taxi_eth_phy_10g_us_gt_ll.sv b/src/eth/rtl/us/taxi_eth_phy_10g_us_gt_ll.sv index 4dbe00a..f15561b 100644 --- a/src/eth/rtl/us/taxi_eth_phy_10g_us_gt_ll.sv +++ b/src/eth/rtl/us/taxi_eth_phy_10g_us_gt_ll.sv @@ -388,7 +388,7 @@ logic tx_req_stall_reg = 1'b0; assign serdes_tx_gbx_req_sync = tx_req_sync_reg; assign serdes_tx_gbx_req_stall = tx_req_stall_reg; -always @(posedge tx_clk) begin +always_ff @(posedge tx_clk) begin tx_req_sync_reg <= 1'b0; tx_req_stall_reg <= 1'b0; @@ -407,7 +407,7 @@ logic [6:0] tx_seq_reg = '0; assign gt_txsequence = {1'b0, tx_seq_reg[6:1]}; -always @(posedge tx_clk) begin +always_ff @(posedge tx_clk) begin tx_seq_reg <= tx_seq_reg + 1; if (tx_seq_reg == 65) begin tx_seq_reg <= '0; diff --git a/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.sv b/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.sv index 5dd36b2..f835f73 100644 --- a/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.sv +++ b/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.sv @@ -389,7 +389,7 @@ if (GT_TYPE == "GTY") begin : tx_seq assign serdes_tx_gbx_req_sync = tx_req_sync_reg; assign serdes_tx_gbx_req_stall = tx_req_stall_reg; - always @(posedge tx_clk) begin + always_ff @(posedge tx_clk) begin tx_req_sync_reg <= 1'b0; tx_req_stall_reg <= 1'b0; @@ -408,7 +408,7 @@ if (GT_TYPE == "GTY") begin : tx_seq assign gt_txsequence = {1'b0, tx_seq_reg[6:1]}; - always @(posedge tx_clk) begin + always_ff @(posedge tx_clk) begin tx_seq_reg <= tx_seq_reg + 1; if (tx_seq_reg == 65) begin tx_seq_reg <= '0; @@ -430,7 +430,7 @@ end else begin : tx_seq assign serdes_tx_gbx_req_sync = tx_req_sync_reg; assign serdes_tx_gbx_req_stall = tx_req_stall_reg; - always @(posedge tx_clk) begin + always_ff @(posedge tx_clk) begin tx_req_sync_reg <= 1'b0; tx_req_stall_reg <= 1'b0; @@ -449,7 +449,7 @@ end else begin : tx_seq assign gt_txsequence = {1'b0, tx_seq_reg}; - always @(posedge tx_clk) begin + always_ff @(posedge tx_clk) begin tx_seq_reg <= tx_seq_reg + 1; if (tx_seq_reg == 32) begin tx_seq_reg <= '0; diff --git a/src/io/rtl/taxi_led_sreg.sv b/src/io/rtl/taxi_led_sreg.sv index 628ae7a..9b1ac80 100644 --- a/src/io/rtl/taxi_led_sreg.sv +++ b/src/io/rtl/taxi_led_sreg.sv @@ -82,7 +82,7 @@ sync_inst ( .out(led_sync) ); -always @(posedge clk) begin +always_ff @(posedge clk) begin enable_reg <= 1'b0; if (prescale_count_reg != 0) begin diff --git a/src/lfsr/rtl/taxi_lfsr_prbs_gen.sv b/src/lfsr/rtl/taxi_lfsr_prbs_gen.sv index 340b492..1275d2f 100644 --- a/src/lfsr/rtl/taxi_lfsr_prbs_gen.sv +++ b/src/lfsr/rtl/taxi_lfsr_prbs_gen.sv @@ -170,7 +170,7 @@ lfsr_inst ( .state_out(lfsr_state) ); -always @(posedge clk) begin +always_ff @(posedge clk) begin if (enable) begin state_reg <= lfsr_state; end diff --git a/src/zircon/rtl/zircon_ip_rx_parse.sv b/src/zircon/rtl/zircon_ip_rx_parse.sv index 252b1b1..2dba4ce 100644 --- a/src/zircon/rtl/zircon_ip_rx_parse.sv +++ b/src/zircon/rtl/zircon_ip_rx_parse.sv @@ -245,7 +245,7 @@ if (HASH_EN) begin : rss_hash end endfunction - always @(posedge clk) begin + always_ff @(posedge clk) begin if (hash_step) begin hash_reg <= hash_reg ^ hash_toep32(pkt_data_be, key_reg); end