Reorganize repository
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
64
src/axis/tb/taxi_axis_adapter/Makefile
Normal file
64
src/axis/tb/taxi_axis_adapter/Makefile
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@@ -0,0 +1,64 @@
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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#
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# Copyright (c) 2021-2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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RTL_DIR = ../../rtl
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LIB_DIR = ../../lib
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TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
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DUT = taxi_axis_adapter
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COCOTB_TEST_MODULES = test_$(DUT)
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COCOTB_TOPLEVEL = test_$(DUT)
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MODULE = $(COCOTB_TEST_MODULES)
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TOPLEVEL = $(COCOTB_TOPLEVEL)
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VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
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VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
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VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
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# module parameters
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export PARAM_S_DATA_W := 8
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export PARAM_S_KEEP_EN := $(shell expr $(PARAM_S_DATA_W) \> 8 )
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export PARAM_S_KEEP_W := $(shell expr \( $(PARAM_S_DATA_W) + 7 \) / 8 )
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export PARAM_S_STRB_EN := 0
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export PARAM_M_DATA_W := 8
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export PARAM_M_KEEP_EN := $(shell expr $(PARAM_M_DATA_W) \> 8 )
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export PARAM_M_KEEP_W := $(shell expr \( $(PARAM_M_DATA_W) + 7 \) / 8 )
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export PARAM_M_STRB_EN := $(PARAM_S_STRB_EN)
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export PARAM_ID_EN := 1
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export PARAM_ID_W := 8
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export PARAM_DEST_EN := 1
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export PARAM_DEST_W := 8
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export PARAM_USER_EN := 1
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export PARAM_USER_W := 1
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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VERILATOR_TRACE = 1
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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266
src/axis/tb/taxi_axis_adapter/test_taxi_axis_adapter.py
Normal file
266
src/axis/tb/taxi_axis_adapter/test_taxi_axis_adapter.py
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@@ -0,0 +1,266 @@
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#!/usr/bin/env python
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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"""
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Copyright (c) 2021-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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"""
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import itertools
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import logging
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import os
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import random
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import cocotb_test.simulator
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import pytest
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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from cocotb.regression import TestFactory
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from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
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class TB(object):
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
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self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
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self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
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def set_idle_generator(self, generator=None):
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if generator:
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self.source.set_pause_generator(generator())
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def set_backpressure_generator(self, generator=None):
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if generator:
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self.sink.set_pause_generator(generator())
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async def reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
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tb = TB(dut)
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id_count = 2**len(tb.source.bus.tid)
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cur_id = 1
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await tb.reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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test_frames = []
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for test_data in [payload_data(x) for x in payload_lengths()]:
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test_frame = AxiStreamFrame(test_data)
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test_frame.tid = cur_id
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test_frame.tdest = cur_id
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# set tkeep to all zeros when disabled to verify correct handling
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if not int(dut.S_KEEP_EN.value):
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test_frame.tkeep = [0]*len(test_data)
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test_frames.append(test_frame)
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await tb.source.send(test_frame)
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cur_id = (cur_id + 1) % id_count
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for test_frame in test_frames:
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rx_frame = await tb.sink.recv()
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assert rx_frame.tdata == test_frame.tdata
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assert rx_frame.tid == test_frame.tid
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assert rx_frame.tdest == test_frame.tdest
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assert not rx_frame.tuser
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assert tb.sink.empty()
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_test_tuser_assert(dut):
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tb = TB(dut)
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await tb.reset()
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test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
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test_frame = AxiStreamFrame(test_data, tuser=1)
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await tb.source.send(test_frame)
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rx_frame = await tb.sink.recv()
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assert rx_frame.tdata == test_data
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assert rx_frame.tuser
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assert tb.sink.empty()
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
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tb = TB(dut)
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byte_lanes = max(tb.source.byte_lanes, tb.sink.byte_lanes)
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id_count = 2**len(tb.source.bus.tid)
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cur_id = 1
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await tb.reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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test_frames = []
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for k in range(128):
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length = random.randint(1, byte_lanes*16)
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test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
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test_frame = AxiStreamFrame(test_data)
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test_frame.tid = cur_id
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test_frame.tdest = cur_id
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test_frames.append(test_frame)
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await tb.source.send(test_frame)
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cur_id = (cur_id + 1) % id_count
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for test_frame in test_frames:
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rx_frame = await tb.sink.recv()
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assert rx_frame.tdata == test_frame.tdata
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assert rx_frame.tid == test_frame.tid
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assert rx_frame.tdest == test_frame.tdest
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assert not rx_frame.tuser
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assert tb.sink.empty()
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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def cycle_pause():
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return itertools.cycle([1, 1, 1, 0])
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def size_list():
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data_width = max(len(cocotb.top.s_axis.tdata), len(cocotb.top.m_axis.tdata))
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byte_width = data_width // 8
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return list(range(1, byte_width*4+1))+[512]+[1]*64
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def incrementing_payload(length):
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return bytearray(itertools.islice(itertools.cycle(range(256)), length))
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if cocotb.SIM_NAME:
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factory = TestFactory(run_test)
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factory.add_option("payload_lengths", [size_list])
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factory.add_option("payload_data", [incrementing_payload])
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factory.add_option("idle_inserter", [None, cycle_pause])
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factory.add_option("backpressure_inserter", [None, cycle_pause])
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factory.generate_tests()
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for test in [run_test_tuser_assert]:
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factory = TestFactory(test)
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factory.generate_tests()
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factory = TestFactory(run_stress_test)
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factory.add_option("idle_inserter", [None, cycle_pause])
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factory.add_option("backpressure_inserter", [None, cycle_pause])
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factory.generate_tests()
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# cocotb-test
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tests_dir = os.path.dirname(__file__)
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rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
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lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
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taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
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def process_f_files(files):
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lst = {}
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for f in files:
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if f[-2:].lower() == '.f':
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with open(f, 'r') as fp:
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l = fp.read().split()
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for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
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lst[os.path.basename(f)] = f
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else:
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lst[os.path.basename(f)] = f
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return list(lst.values())
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@pytest.mark.parametrize("m_data_width", [8, 16, 32])
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@pytest.mark.parametrize("s_data_width", [8, 16, 32])
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def test_taxi_axis_register(request, s_data_width, m_data_width):
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dut = "taxi_axis_adapter"
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module = os.path.splitext(os.path.basename(__file__))[0]
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toplevel = module
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verilog_sources = [
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os.path.join(tests_dir, f"{toplevel}.sv"),
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os.path.join(rtl_dir, f"{dut}.sv"),
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os.path.join(rtl_dir, "taxi_axis_if.sv"),
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]
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verilog_sources = process_f_files(verilog_sources)
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parameters = {}
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parameters['S_DATA_W'] = s_data_width
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parameters['S_KEEP_EN'] = int(parameters['S_DATA_W'] > 8)
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parameters['S_KEEP_W'] = (parameters['S_DATA_W'] + 7) // 8
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parameters['S_STRB_EN'] = 0
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parameters['M_DATA_W'] = m_data_width
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parameters['M_KEEP_EN'] = int(parameters['M_DATA_W'] > 8)
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parameters['M_KEEP_W'] = (parameters['M_DATA_W'] + 7) // 8
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parameters['M_STRB_EN'] = parameters['S_STRB_EN']
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parameters['ID_EN'] = 1
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parameters['ID_W'] = 8
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parameters['DEST_EN'] = 1
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parameters['DEST_W'] = 8
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parameters['USER_EN'] = 1
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parameters['USER_W'] = 1
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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simulator="verilator",
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python_search=[tests_dir],
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verilog_sources=verilog_sources,
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toplevel=toplevel,
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module=module,
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parameters=parameters,
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sim_build=sim_build,
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extra_env=extra_env,
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)
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88
src/axis/tb/taxi_axis_adapter/test_taxi_axis_adapter.sv
Normal file
88
src/axis/tb/taxi_axis_adapter/test_taxi_axis_adapter.sv
Normal file
@@ -0,0 +1,88 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
|
||||
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||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
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Authors:
|
||||
- Alex Forencich
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|
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4-Stream FIFO testbench
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*/
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module test_taxi_axis_adapter #
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(
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/* verilator lint_off WIDTHTRUNC */
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parameter S_DATA_W = 8,
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parameter logic S_KEEP_EN = (S_DATA_W>8),
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parameter S_KEEP_W = ((S_DATA_W+7)/8),
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parameter logic S_STRB_EN = 0,
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parameter M_DATA_W = 8,
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parameter logic M_KEEP_EN = (M_DATA_W>8),
|
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parameter M_KEEP_W = ((M_DATA_W+7)/8),
|
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parameter logic M_STRB_EN = 0,
|
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parameter logic ID_EN = 0,
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parameter ID_W = 8,
|
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parameter logic DEST_EN = 0,
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parameter DEST_W = 8,
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parameter logic USER_EN = 1,
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parameter USER_W = 1
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/* verilator lint_on WIDTHTRUNC */
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)
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();
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logic clk;
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logic rst;
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taxi_axis_if #(
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.DATA_W(S_DATA_W),
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.KEEP_EN(S_KEEP_EN),
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.KEEP_W(S_KEEP_W),
|
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.STRB_EN(S_STRB_EN),
|
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.LAST_EN(1'b1),
|
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.ID_EN(ID_EN),
|
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.ID_W(ID_W),
|
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.DEST_EN(DEST_EN),
|
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.DEST_W(DEST_W),
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.USER_EN(USER_EN),
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.USER_W(USER_W)
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) s_axis();
|
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taxi_axis_if #(
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.DATA_W(M_DATA_W),
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.KEEP_EN(M_KEEP_EN),
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.KEEP_W(M_KEEP_W),
|
||||
.STRB_EN(M_STRB_EN),
|
||||
.LAST_EN(1'b1),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) m_axis();
|
||||
|
||||
taxi_axis_adapter
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uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
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.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
65
src/axis/tb/taxi_axis_arb_mux/Makefile
Normal file
65
src/axis/tb/taxi_axis_arb_mux/Makefile
Normal file
@@ -0,0 +1,65 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_arb_mux
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_S_COUNT := 4
|
||||
export PARAM_DATA_W := 8
|
||||
export PARAM_KEEP_EN := $(shell expr $(PARAM_DATA_W) \> 8 )
|
||||
export PARAM_KEEP_W := $(shell expr \( $(PARAM_DATA_W) + 7 \) / 8 )
|
||||
export PARAM_STRB_EN := 0
|
||||
export PARAM_LAST_EN := 1
|
||||
export PARAM_ID_EN := 1
|
||||
export PARAM_S_ID_W := 8
|
||||
export PARAM_M_ID_W := $(shell python -c "print($(PARAM_S_ID_W) + ($(PARAM_S_COUNT)-1).bit_length())")
|
||||
export PARAM_DEST_EN := 1
|
||||
export PARAM_DEST_W := 8
|
||||
export PARAM_USER_EN := 1
|
||||
export PARAM_USER_W := 1
|
||||
export PARAM_UPDATE_TID := 1
|
||||
export PARAM_ARB_ROUND_ROBIN := 0
|
||||
export PARAM_ARB_LSB_HIGH_PRIO := 1
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
365
src/axis/tb/taxi_axis_arb_mux/test_taxi_axis_arb_mux.py
Normal file
365
src/axis/tb/taxi_axis_arb_mux/test_taxi_axis_arb_mux.py
Normal file
@@ -0,0 +1,365 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Event
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = [AxiStreamSource(AxiStreamBus.from_entity(bus), dut.clk, dut.rst) for bus in dut.s_axis]
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
for source in self.source:
|
||||
source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None, port=0):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_width = len(tb.source[0].bus.tid)
|
||||
id_count = 2**id_width
|
||||
id_mask = id_count-1
|
||||
|
||||
src_width = (len(tb.source)-1).bit_length()
|
||||
src_mask = 2**src_width-1 if src_width else 0
|
||||
src_shift = id_width-src_width
|
||||
max_count = 2**src_shift
|
||||
count_mask = max_count-1
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id | (port << src_shift)
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source[port].send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % max_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert (rx_frame.tid & id_mask) == test_frame.tid
|
||||
assert ((rx_frame.tid >> src_shift) & src_mask) == port
|
||||
assert (rx_frame.tid >> id_width) == port
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_tuser_assert(dut, port=0):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data, tuser=1)
|
||||
await tb.source[port].send(test_frame)
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_arb_test(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.source[0].byte_lanes
|
||||
id_width = len(tb.source[0].bus.tid)
|
||||
id_count = 2**id_width
|
||||
id_mask = id_count-1
|
||||
|
||||
src_width = (len(tb.source)-1).bit_length()
|
||||
src_mask = 2**src_width-1 if src_width else 0
|
||||
src_shift = id_width-src_width
|
||||
max_count = 2**src_shift
|
||||
count_mask = max_count-1
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_frames = []
|
||||
|
||||
length = byte_lanes*16
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
for k in range(5):
|
||||
test_frame = AxiStreamFrame(test_data, tx_complete=Event())
|
||||
|
||||
src_ind = 0
|
||||
|
||||
if k == 0:
|
||||
src_ind = 0
|
||||
elif k == 4:
|
||||
await test_frames[1].tx_complete.wait()
|
||||
for j in range(8):
|
||||
await RisingEdge(dut.clk)
|
||||
src_ind = 0
|
||||
else:
|
||||
src_ind = 1
|
||||
|
||||
test_frame.tid = cur_id | (src_ind << src_shift)
|
||||
test_frame.tdest = 0
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source[src_ind].send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % max_count
|
||||
|
||||
for k in [0, 1, 2, 4, 3]:
|
||||
test_frame = test_frames[k]
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert (rx_frame.tid & id_mask) == test_frame.tid
|
||||
assert ((rx_frame.tid >> src_shift) & src_mask) == (rx_frame.tid >> id_width)
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.source[0].byte_lanes
|
||||
id_width = len(tb.source[0].bus.tid)
|
||||
id_count = 2**id_width
|
||||
id_mask = id_count-1
|
||||
|
||||
src_width = (len(tb.source)-1).bit_length()
|
||||
src_mask = 2**src_width-1 if src_width else 0
|
||||
src_shift = id_width-src_width
|
||||
max_count = 2**src_shift
|
||||
count_mask = max_count-1
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = [list() for x in tb.source]
|
||||
|
||||
for p in range(len(tb.source)):
|
||||
for k in range(128):
|
||||
length = random.randint(1, byte_lanes*16)
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id | (p << src_shift)
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames[p].append(test_frame)
|
||||
await tb.source[p].send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % max_count
|
||||
|
||||
while any(test_frames):
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
test_frame = None
|
||||
|
||||
for lst in test_frames:
|
||||
if lst and lst[0].tid == (rx_frame.tid & id_mask):
|
||||
test_frame = lst.pop(0)
|
||||
break
|
||||
|
||||
assert test_frame is not None
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert (rx_frame.tid & id_mask) == test_frame.tid
|
||||
assert ((rx_frame.tid >> src_shift) & src_mask) == (rx_frame.tid >> id_width)
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = len(cocotb.top.m_axis.tdata)
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
ports = len(cocotb.top.s_axis)
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.add_option("port", list(range(ports)))
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [run_test_tuser_assert]:
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("port", list(range(ports)))
|
||||
factory.generate_tests()
|
||||
|
||||
if ports > 1:
|
||||
factory = TestFactory(run_arb_test)
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("round_robin", [0, 1])
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32])
|
||||
@pytest.mark.parametrize("s_count", [1, 4])
|
||||
def test_taxi_axis_arb_mux(request, s_count, data_w, round_robin):
|
||||
dut = "taxi_axis_arb_mux"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['S_COUNT'] = s_count
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
|
||||
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
|
||||
parameters['STRB_EN'] = 0
|
||||
parameters['LAST_EN'] = 1
|
||||
parameters['ID_EN'] = 1
|
||||
parameters['S_ID_W'] = 8
|
||||
parameters['M_ID_W'] = parameters['S_ID_W'] + (s_count-1).bit_length()
|
||||
parameters['DEST_EN'] = 1
|
||||
parameters['DEST_W'] = 8
|
||||
parameters['USER_EN'] = 1
|
||||
parameters['USER_W'] = 1
|
||||
parameters['UPDATE_TID'] = 1
|
||||
parameters['ARB_ROUND_ROBIN'] = round_robin
|
||||
parameters['ARB_LSB_HIGH_PRIO'] = 1
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
95
src/axis/tb/taxi_axis_arb_mux/test_taxi_axis_arb_mux.sv
Normal file
95
src/axis/tb/taxi_axis_arb_mux/test_taxi_axis_arb_mux.sv
Normal file
@@ -0,0 +1,95 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream arbitrated multiplexer testbench
|
||||
*/
|
||||
module test_taxi_axis_arb_mux #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter S_COUNT = 4,
|
||||
parameter DATA_W = 8,
|
||||
parameter logic KEEP_EN = (DATA_W>8),
|
||||
parameter KEEP_W = ((DATA_W+7)/8),
|
||||
parameter logic STRB_EN = 1'b0,
|
||||
parameter logic LAST_EN = 1'b1,
|
||||
parameter logic ID_EN = 1'b0,
|
||||
parameter S_ID_W = 8,
|
||||
parameter M_ID_W = S_ID_W+$clog2(S_COUNT),
|
||||
parameter logic DEST_EN = 1'b0,
|
||||
parameter DEST_W = 8,
|
||||
parameter logic USER_EN = 1'b1,
|
||||
parameter USER_W = 1,
|
||||
parameter logic UPDATE_TID = 1'b0,
|
||||
parameter logic ARB_ROUND_ROBIN = 1'b0,
|
||||
parameter logic ARB_LSB_HIGH_PRIO = 1'b1
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(STRB_EN),
|
||||
.LAST_EN(LAST_EN),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(S_ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis[S_COUNT]();
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(STRB_EN),
|
||||
.LAST_EN(LAST_EN),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(M_ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) m_axis();
|
||||
|
||||
taxi_axis_arb_mux #(
|
||||
.S_COUNT(S_COUNT),
|
||||
.UPDATE_TID(UPDATE_TID),
|
||||
.ARB_ROUND_ROBIN(ARB_ROUND_ROBIN),
|
||||
.ARB_LSB_HIGH_PRIO(ARB_LSB_HIGH_PRIO)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
72
src/axis/tb/taxi_axis_async_fifo/Makefile
Normal file
72
src/axis/tb/taxi_axis_async_fifo/Makefile
Normal file
@@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_async_fifo
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_W := 8
|
||||
export PARAM_KEEP_EN := $(shell echo $$(( $(PARAM_DATA_W) > 8 )))
|
||||
export PARAM_KEEP_W := $(shell echo $$(( ( $(PARAM_DATA_W) + 7 ) / 8 )))
|
||||
export PARAM_STRB_EN := 0
|
||||
export PARAM_DEPTH := $(shell echo $$(( 1024 * $(PARAM_KEEP_W) )))
|
||||
export PARAM_LAST_EN := 1
|
||||
export PARAM_ID_EN := 1
|
||||
export PARAM_ID_W := 8
|
||||
export PARAM_DEST_EN := 1
|
||||
export PARAM_DEST_W := 8
|
||||
export PARAM_USER_EN := 1
|
||||
export PARAM_USER_W := 1
|
||||
export PARAM_RAM_PIPELINE := 1
|
||||
export PARAM_OUTPUT_FIFO_EN := 0
|
||||
export PARAM_FRAME_FIFO := 1
|
||||
export PARAM_USER_BAD_FRAME_VALUE := 1
|
||||
export PARAM_USER_BAD_FRAME_MASK := 1
|
||||
export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
|
||||
export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
|
||||
export PARAM_DROP_WHEN_FULL := 0
|
||||
export PARAM_MARK_WHEN_FULL := 0
|
||||
export PARAM_PAUSE_EN := 1
|
||||
export PARAM_FRAME_PAUSE := 1
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
735
src/axis/tb/taxi_axis_async_fifo/test_taxi_axis_async_fifo.py
Normal file
735
src/axis/tb/taxi_axis_async_fifo/test_taxi_axis_async_fifo.py
Normal file
@@ -0,0 +1,735 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
s_clk = int(os.getenv("S_CLK_PERIOD", "10"))
|
||||
m_clk = int(os.getenv("M_CLK_PERIOD", "11"))
|
||||
|
||||
cocotb.start_soon(Clock(dut.s_clk, s_clk, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.m_clk, m_clk, units="ns").start())
|
||||
|
||||
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.s_clk, dut.s_rst)
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.m_clk, dut.m_rst)
|
||||
|
||||
dut.s_pause_req.setimmediatevalue(0)
|
||||
dut.m_pause_req.setimmediatevalue(0)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.m_rst.setimmediatevalue(0)
|
||||
self.dut.s_rst.setimmediatevalue(0)
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
self.dut.m_rst.value = 1
|
||||
self.dut.s_rst.value = 1
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
self.dut.m_rst.value = 0
|
||||
self.dut.s_rst.value = 0
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
|
||||
async def reset_source(self):
|
||||
self.dut.s_rst.setimmediatevalue(0)
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
self.dut.s_rst.value = 1
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
self.dut.s_rst.value = 0
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
|
||||
async def reset_sink(self):
|
||||
self.dut.m_rst.setimmediatevalue(0)
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.m_clk)
|
||||
self.dut.m_rst.value = 1
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.m_clk)
|
||||
self.dut.m_rst.value = 0
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.m_clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_tuser_assert(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data, tuser=1)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
if int(dut.DROP_BAD_FRAME.value):
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
else:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause_source_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 512))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(1024):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_source()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause_sink_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_sink()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_shift_in_source_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(8):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_source()
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
if int(dut.FRAME_FIFO.value):
|
||||
assert tb.sink.empty()
|
||||
else:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_shift_in_sink_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(8):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_sink()
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_shift_out_source_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
await RisingEdge(dut.m_axis.tvalid)
|
||||
|
||||
for k in range(8):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_source()
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_shift_out_sink_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
await RisingEdge(dut.m_axis.tvalid)
|
||||
|
||||
for k in range(8):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_sink()
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_pause(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.source.byte_lanes
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 16*byte_lanes))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
|
||||
for k in range(16):
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(60):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
dut.m_pause_req.value = 1
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
dut.m_pause_req.value = 0
|
||||
|
||||
for k in range(60):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
dut.s_pause_req.value = 1
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
dut.s_pause_req.value = 0
|
||||
|
||||
for k in range(16):
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_overflow(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
depth = int(dut.DEPTH.value)
|
||||
byte_lanes = tb.source.byte_lanes
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
size = (16*byte_lanes)
|
||||
count = depth*2 // size
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), size))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
for k in range(count):
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range((depth//byte_lanes)*3):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
|
||||
assert tb.source.idle()
|
||||
else:
|
||||
assert not tb.source.idle()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
|
||||
for k in range((depth//byte_lanes)*3):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
rx_count = 0
|
||||
|
||||
while not tb.sink.empty():
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if int(dut.MARK_WHEN_FULL.value) and rx_frame.tuser:
|
||||
continue
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
rx_count += 1
|
||||
|
||||
assert rx_count < count
|
||||
|
||||
else:
|
||||
for k in range(count):
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_oversize(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
depth = int(dut.DEPTH.value)
|
||||
byte_lanes = tb.source.byte_lanes
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), depth*2))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range((depth//byte_lanes)*2):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
if int(dut.DROP_OVERSIZE_FRAME.value):
|
||||
for k in range((depth//byte_lanes)*2):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
else:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if int(dut.MARK_WHEN_FULL.value):
|
||||
assert rx_frame.tuser
|
||||
else:
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.source.byte_lanes
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for k in range(512):
|
||||
length = random.randint(1, byte_lanes*16)
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
|
||||
cycles = 0
|
||||
while cycles < 100:
|
||||
cycles += 1
|
||||
if not tb.source.idle() or int(dut.s_axis.tvalid.value) or int(dut.m_axis.tvalid.value) or int(dut.m_status_depth.value):
|
||||
cycles = 0
|
||||
await RisingEdge(dut.m_clk)
|
||||
|
||||
while not tb.sink.empty():
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if int(dut.MARK_WHEN_FULL.value) and rx_frame.tuser:
|
||||
continue
|
||||
|
||||
assert not rx_frame.tuser
|
||||
|
||||
while True:
|
||||
test_frame = test_frames.pop(0)
|
||||
if rx_frame.tid == test_frame.tid and rx_frame.tdest == test_frame.tdest and rx_frame.tdata == test_frame.tdata:
|
||||
break
|
||||
|
||||
assert len(test_frames) < 512
|
||||
|
||||
else:
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = len(cocotb.top.m_axis.tdata)
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [
|
||||
run_test_tuser_assert,
|
||||
run_test_init_sink_pause,
|
||||
run_test_init_sink_pause_reset,
|
||||
run_test_init_sink_pause_source_reset,
|
||||
run_test_init_sink_pause_sink_reset,
|
||||
run_test_shift_in_source_reset,
|
||||
run_test_shift_in_sink_reset,
|
||||
run_test_shift_out_source_reset,
|
||||
run_test_shift_out_sink_reset,
|
||||
run_test_pause,
|
||||
run_test_overflow,
|
||||
run_test_oversize
|
||||
]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize(("s_clk", "m_clk"), [(10, 10), (10, 11), (11, 10)])
|
||||
@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame",
|
||||
"drop_when_full", "mark_when_full"),
|
||||
[(0, 0, 0, 0, 0), (1, 0, 0, 0, 0), (1, 1, 0, 0, 0), (1, 1, 1, 0, 0),
|
||||
(1, 1, 1, 1, 0), (0, 0, 0, 0, 1)])
|
||||
@pytest.mark.parametrize(("ram_pipeline", "output_fifo"),
|
||||
[(0, 0), (1, 0), (4, 0), (0, 1), (1, 1), (4, 1)])
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32, 64])
|
||||
def test_taxi_axis_async_fifo(request, data_w, ram_pipeline, output_fifo,
|
||||
frame_fifo, drop_oversize_frame, drop_bad_frame,
|
||||
drop_when_full, mark_when_full, s_clk, m_clk):
|
||||
|
||||
dut = "taxi_axis_async_fifo"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
|
||||
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
|
||||
parameters['STRB_EN'] = 0
|
||||
parameters['DEPTH'] = 1024 * parameters['KEEP_W']
|
||||
parameters['LAST_EN'] = 1
|
||||
parameters['ID_EN'] = 1
|
||||
parameters['ID_W'] = 8
|
||||
parameters['DEST_EN'] = 1
|
||||
parameters['DEST_W'] = 8
|
||||
parameters['USER_EN'] = 1
|
||||
parameters['USER_W'] = 1
|
||||
parameters['RAM_PIPELINE'] = ram_pipeline
|
||||
parameters['OUTPUT_FIFO_EN'] = output_fifo
|
||||
parameters['FRAME_FIFO'] = frame_fifo
|
||||
parameters['USER_BAD_FRAME_VALUE'] = 1
|
||||
parameters['USER_BAD_FRAME_MASK'] = 1
|
||||
parameters['DROP_OVERSIZE_FRAME'] = drop_oversize_frame
|
||||
parameters['DROP_BAD_FRAME'] = drop_bad_frame
|
||||
parameters['DROP_WHEN_FULL'] = drop_when_full
|
||||
parameters['MARK_WHEN_FULL'] = mark_when_full
|
||||
parameters['PAUSE_EN'] = 1
|
||||
parameters['FRAME_PAUSE'] = 1
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
extra_env['S_CLK_PERIOD'] = str(s_clk)
|
||||
extra_env['M_CLK_PERIOD'] = str(m_clk)
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
138
src/axis/tb/taxi_axis_async_fifo/test_taxi_axis_async_fifo.sv
Normal file
138
src/axis/tb/taxi_axis_async_fifo/test_taxi_axis_async_fifo.sv
Normal file
@@ -0,0 +1,138 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream asynchronous FIFO testbench
|
||||
*/
|
||||
module test_taxi_axis_async_fifo #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DEPTH = 4096,
|
||||
parameter DATA_W = 8,
|
||||
parameter logic KEEP_EN = (DATA_W>8),
|
||||
parameter KEEP_W = ((DATA_W+7)/8),
|
||||
parameter logic STRB_EN = 1'b0,
|
||||
parameter logic LAST_EN = 1'b1,
|
||||
parameter logic ID_EN = 1'b0,
|
||||
parameter ID_W = 8,
|
||||
parameter logic DEST_EN = 1'b0,
|
||||
parameter DEST_W = 8,
|
||||
parameter logic USER_EN = 1'b1,
|
||||
parameter USER_W = 1,
|
||||
parameter RAM_PIPELINE = 1,
|
||||
parameter logic OUTPUT_FIFO_EN = 1'b0,
|
||||
parameter logic FRAME_FIFO = 1'b0,
|
||||
parameter logic [USER_W-1:0] USER_BAD_FRAME_VALUE = 1'b1,
|
||||
parameter logic [USER_W-1:0] USER_BAD_FRAME_MASK = 1'b1,
|
||||
parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
|
||||
parameter logic DROP_BAD_FRAME = 1'b0,
|
||||
parameter logic DROP_WHEN_FULL = 1'b0,
|
||||
parameter logic MARK_WHEN_FULL = 1'b0,
|
||||
parameter logic PAUSE_EN = 1'b0,
|
||||
parameter logic FRAME_PAUSE = FRAME_FIFO
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic s_clk;
|
||||
logic s_rst;
|
||||
|
||||
logic m_clk;
|
||||
logic m_rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(STRB_EN),
|
||||
.LAST_EN(LAST_EN),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis(), m_axis();
|
||||
|
||||
logic s_pause_req;
|
||||
logic s_pause_ack;
|
||||
logic m_pause_req;
|
||||
logic m_pause_ack;
|
||||
|
||||
logic [$clog2(DEPTH):0] s_status_depth;
|
||||
logic [$clog2(DEPTH):0] s_status_depth_commit;
|
||||
logic s_status_overflow;
|
||||
logic s_status_bad_frame;
|
||||
logic s_status_good_frame;
|
||||
logic [$clog2(DEPTH):0] m_status_depth;
|
||||
logic [$clog2(DEPTH):0] m_status_depth_commit;
|
||||
logic m_status_overflow;
|
||||
logic m_status_bad_frame;
|
||||
logic m_status_good_frame;
|
||||
|
||||
taxi_axis_async_fifo #(
|
||||
.DEPTH(DEPTH),
|
||||
.RAM_PIPELINE(RAM_PIPELINE),
|
||||
.OUTPUT_FIFO_EN(OUTPUT_FIFO_EN),
|
||||
.FRAME_FIFO(FRAME_FIFO),
|
||||
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
|
||||
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
|
||||
.DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME),
|
||||
.DROP_BAD_FRAME(DROP_BAD_FRAME),
|
||||
.DROP_WHEN_FULL(DROP_WHEN_FULL),
|
||||
.MARK_WHEN_FULL(MARK_WHEN_FULL),
|
||||
.PAUSE_EN(PAUSE_EN),
|
||||
.FRAME_PAUSE(FRAME_PAUSE)
|
||||
)
|
||||
uut (
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_clk(s_clk),
|
||||
.s_rst(s_rst),
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_clk(m_clk),
|
||||
.m_rst(m_rst),
|
||||
.m_axis(m_axis),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.s_pause_req(s_pause_req),
|
||||
.s_pause_ack(s_pause_ack),
|
||||
.m_pause_req(m_pause_req),
|
||||
.m_pause_ack(m_pause_ack),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.s_status_depth(s_status_depth),
|
||||
.s_status_depth_commit(s_status_depth_commit),
|
||||
.s_status_overflow(s_status_overflow),
|
||||
.s_status_bad_frame(s_status_bad_frame),
|
||||
.s_status_good_frame(s_status_good_frame),
|
||||
.m_status_depth(m_status_depth),
|
||||
.m_status_depth_commit(m_status_depth_commit),
|
||||
.m_status_overflow(m_status_overflow),
|
||||
.m_status_bad_frame(m_status_bad_frame),
|
||||
.m_status_good_frame(m_status_good_frame)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
75
src/axis/tb/taxi_axis_async_fifo_adapter/Makefile
Normal file
75
src/axis/tb/taxi_axis_async_fifo_adapter/Makefile
Normal file
@@ -0,0 +1,75 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_async_fifo_adapter
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_S_DATA_W := 8
|
||||
export PARAM_S_KEEP_EN := $(shell echo $$(( $(PARAM_S_DATA_W) > 8 )))
|
||||
export PARAM_S_KEEP_W := $(shell echo $$(( ( $(PARAM_S_DATA_W) + 7 ) / 8 )))
|
||||
export PARAM_S_STRB_EN := 0
|
||||
export PARAM_M_DATA_W := 8
|
||||
export PARAM_M_KEEP_EN := $(shell echo $$(( $(PARAM_M_DATA_W) > 8 )))
|
||||
export PARAM_M_KEEP_W := $(shell echo $$(( ( $(PARAM_M_DATA_W) + 7 ) / 8 )))
|
||||
export PARAM_M_STRB_EN := $(PARAM_S_STRB_EN)
|
||||
export PARAM_DEPTH := $(shell echo $$(( 1024 * ($(PARAM_S_KEEP_W) > $(PARAM_M_KEEP_W) ? $(PARAM_S_KEEP_W) : $(PARAM_M_KEEP_W)) )))
|
||||
export PARAM_ID_EN := 1
|
||||
export PARAM_ID_W := 8
|
||||
export PARAM_DEST_EN := 1
|
||||
export PARAM_DEST_W := 8
|
||||
export PARAM_USER_EN := 1
|
||||
export PARAM_USER_W := 1
|
||||
export PARAM_RAM_PIPELINE := 1
|
||||
export PARAM_OUTPUT_FIFO_EN := 0
|
||||
export PARAM_FRAME_FIFO := 1
|
||||
export PARAM_USER_BAD_FRAME_VALUE := 1
|
||||
export PARAM_USER_BAD_FRAME_MASK := 1
|
||||
export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
|
||||
export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
|
||||
export PARAM_DROP_WHEN_FULL := 0
|
||||
export PARAM_MARK_WHEN_FULL := 0
|
||||
export PARAM_PAUSE_EN := 1
|
||||
export PARAM_FRAME_PAUSE := 1
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
@@ -0,0 +1,731 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
s_clk = int(os.getenv("S_CLK_PERIOD", "10"))
|
||||
m_clk = int(os.getenv("M_CLK_PERIOD", "11"))
|
||||
|
||||
cocotb.start_soon(Clock(dut.s_clk, s_clk, units="ns").start())
|
||||
cocotb.start_soon(Clock(dut.m_clk, m_clk, units="ns").start())
|
||||
|
||||
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.s_clk, dut.s_rst)
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.m_clk, dut.m_rst)
|
||||
|
||||
dut.s_pause_req.setimmediatevalue(0)
|
||||
dut.m_pause_req.setimmediatevalue(0)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.m_rst.setimmediatevalue(0)
|
||||
self.dut.s_rst.setimmediatevalue(0)
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
self.dut.m_rst.value = 1
|
||||
self.dut.s_rst.value = 1
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
self.dut.m_rst.value = 0
|
||||
self.dut.s_rst.value = 0
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
|
||||
async def reset_source(self):
|
||||
self.dut.s_rst.setimmediatevalue(0)
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
self.dut.s_rst.value = 1
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
self.dut.s_rst.value = 0
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.s_clk)
|
||||
|
||||
async def reset_sink(self):
|
||||
self.dut.m_rst.setimmediatevalue(0)
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.m_clk)
|
||||
self.dut.m_rst.value = 1
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.m_clk)
|
||||
self.dut.m_rst.value = 0
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.m_clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_tuser_assert(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data, tuser=1)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
if int(dut.DROP_BAD_FRAME.value):
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
else:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause_source_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_source()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause_sink_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_sink()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_shift_in_source_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(8):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_source()
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
if int(dut.FRAME_FIFO.value):
|
||||
assert tb.sink.empty()
|
||||
else:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_shift_in_sink_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(8):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_sink()
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_shift_out_source_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
await RisingEdge(dut.m_axis.tvalid)
|
||||
|
||||
for k in range(8):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_source()
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_shift_out_sink_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
await RisingEdge(dut.m_axis.tvalid)
|
||||
|
||||
for k in range(8):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
await tb.reset_sink()
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_pause(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = max(tb.source.byte_lanes, tb.sink.byte_lanes)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 16*byte_lanes))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
|
||||
for k in range(16):
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(60):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
dut.m_pause_req.value = 1
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
dut.m_pause_req.value = 0
|
||||
|
||||
for k in range(60):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
dut.s_pause_req.value = 1
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
dut.s_pause_req.value = 0
|
||||
|
||||
for k in range(16):
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_overflow(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
depth = int(dut.DEPTH.value)
|
||||
byte_lanes = min(tb.source.byte_lanes, tb.sink.byte_lanes)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
size = (16*byte_lanes)
|
||||
count = depth*2 // size
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), size))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
for k in range(count):
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range((depth//byte_lanes)*3):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
|
||||
assert tb.source.idle()
|
||||
else:
|
||||
assert not tb.source.idle()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
|
||||
for k in range((depth//byte_lanes)*3):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
rx_count = 0
|
||||
|
||||
while not tb.sink.empty():
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if int(dut.MARK_WHEN_FULL.value) and rx_frame.tuser:
|
||||
continue
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
rx_count += 1
|
||||
|
||||
assert rx_count < count
|
||||
|
||||
else:
|
||||
for k in range(count):
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_test_oversize(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
depth = int(dut.DEPTH.value)
|
||||
byte_lanes = min(tb.source.byte_lanes, tb.sink.byte_lanes)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), depth*2))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range((depth//byte_lanes)*2):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
if int(dut.DROP_OVERSIZE_FRAME.value):
|
||||
for k in range((depth//byte_lanes)*2):
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
else:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if int(dut.MARK_WHEN_FULL.value):
|
||||
assert rx_frame.tuser
|
||||
else:
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = max(tb.source.byte_lanes, tb.sink.byte_lanes)
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for k in range(512):
|
||||
length = random.randint(1, byte_lanes*16)
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value:
|
||||
cycles = 0
|
||||
while cycles < 100:
|
||||
cycles += 1
|
||||
if not tb.source.idle() or dut.s_axis.tvalid.value.integer or dut.m_axis.tvalid.value.integer or dut.m_status_depth.value.integer:
|
||||
cycles = 0
|
||||
await RisingEdge(dut.m_clk)
|
||||
|
||||
while not tb.sink.empty():
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if dut.MARK_WHEN_FULL.value and rx_frame.tuser:
|
||||
continue
|
||||
|
||||
assert not rx_frame.tuser
|
||||
|
||||
while True:
|
||||
test_frame = test_frames.pop(0)
|
||||
if rx_frame.tid == test_frame.tid and rx_frame.tdest == test_frame.tdest and rx_frame.tdata == test_frame.tdata:
|
||||
break
|
||||
|
||||
assert len(test_frames) < 512
|
||||
|
||||
else:
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.s_clk)
|
||||
await RisingEdge(dut.s_clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = max(len(cocotb.top.m_axis.tdata), len(cocotb.top.s_axis.tdata))
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [
|
||||
run_test_tuser_assert,
|
||||
run_test_init_sink_pause,
|
||||
run_test_init_sink_pause_reset,
|
||||
run_test_init_sink_pause_source_reset,
|
||||
run_test_init_sink_pause_sink_reset,
|
||||
run_test_shift_in_source_reset,
|
||||
run_test_shift_in_sink_reset,
|
||||
run_test_shift_out_source_reset,
|
||||
run_test_shift_out_sink_reset,
|
||||
run_test_pause,
|
||||
run_test_overflow,
|
||||
run_test_oversize
|
||||
]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame",
|
||||
"drop_when_full", "mark_when_full"),
|
||||
[(0, 0, 0, 0, 0), (1, 0, 0, 0, 0), (1, 1, 0, 0, 0), (1, 1, 1, 0, 0),
|
||||
(1, 1, 1, 1, 0), (0, 0, 0, 0, 1)])
|
||||
@pytest.mark.parametrize("m_data_w", [8, 16, 32])
|
||||
@pytest.mark.parametrize("s_data_w", [8, 16, 32])
|
||||
def test_taxi_axis_async_fifo_adapter(request, s_data_w, m_data_w,
|
||||
frame_fifo, drop_oversize_frame, drop_bad_frame,
|
||||
drop_when_full, mark_when_full):
|
||||
|
||||
dut = "taxi_axis_async_fifo_adapter"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['S_DATA_W'] = s_data_w
|
||||
parameters['S_KEEP_EN'] = int(parameters['S_DATA_W'] > 8)
|
||||
parameters['S_KEEP_W'] = (parameters['S_DATA_W'] + 7) // 8
|
||||
parameters['M_DATA_W'] = m_data_w
|
||||
parameters['M_KEEP_EN'] = int(parameters['M_DATA_W'] > 8)
|
||||
parameters['M_KEEP_W'] = (parameters['M_DATA_W'] + 7) // 8
|
||||
parameters['DEPTH'] = 1024 * max(parameters['S_KEEP_W'], parameters['M_KEEP_W'])
|
||||
parameters['ID_EN'] = 1
|
||||
parameters['ID_W'] = 8
|
||||
parameters['DEST_EN'] = 1
|
||||
parameters['DEST_W'] = 8
|
||||
parameters['USER_EN'] = 1
|
||||
parameters['USER_W'] = 1
|
||||
parameters['RAM_PIPELINE'] = 1
|
||||
parameters['OUTPUT_FIFO_EN'] = 0
|
||||
parameters['FRAME_FIFO'] = frame_fifo
|
||||
parameters['USER_BAD_FRAME_VALUE'] = 1
|
||||
parameters['USER_BAD_FRAME_MASK'] = 1
|
||||
parameters['DROP_OVERSIZE_FRAME'] = drop_oversize_frame
|
||||
parameters['DROP_BAD_FRAME'] = drop_bad_frame
|
||||
parameters['DROP_WHEN_FULL'] = drop_when_full
|
||||
parameters['MARK_WHEN_FULL'] = mark_when_full
|
||||
parameters['PAUSE_EN'] = 1
|
||||
parameters['FRAME_PAUSE'] = 1
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
@@ -0,0 +1,153 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream asynchronous FIFO with width converter testbench
|
||||
*/
|
||||
module test_taxi_axis_async_fifo_adapter #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DEPTH = 4096,
|
||||
parameter S_DATA_W = 8,
|
||||
parameter logic S_KEEP_EN = (S_DATA_W>8),
|
||||
parameter S_KEEP_W = ((S_DATA_W+7)/8),
|
||||
parameter logic S_STRB_EN = 0,
|
||||
parameter M_DATA_W = 8,
|
||||
parameter logic M_KEEP_EN = (M_DATA_W>8),
|
||||
parameter M_KEEP_W = ((M_DATA_W+7)/8),
|
||||
parameter logic M_STRB_EN = 0,
|
||||
parameter logic ID_EN = 1'b0,
|
||||
parameter ID_W = 8,
|
||||
parameter logic DEST_EN = 1'b0,
|
||||
parameter DEST_W = 8,
|
||||
parameter logic USER_EN = 1'b1,
|
||||
parameter USER_W = 1,
|
||||
parameter RAM_PIPELINE = 1,
|
||||
parameter logic OUTPUT_FIFO_EN = 1'b0,
|
||||
parameter logic FRAME_FIFO = 1'b0,
|
||||
parameter logic [USER_W-1:0] USER_BAD_FRAME_VALUE = 1'b1,
|
||||
parameter logic [USER_W-1:0] USER_BAD_FRAME_MASK = 1'b1,
|
||||
parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
|
||||
parameter logic DROP_BAD_FRAME = 1'b0,
|
||||
parameter logic DROP_WHEN_FULL = 1'b0,
|
||||
parameter logic MARK_WHEN_FULL = 1'b0,
|
||||
parameter logic PAUSE_EN = 1'b0,
|
||||
parameter logic FRAME_PAUSE = FRAME_FIFO
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic s_clk;
|
||||
logic s_rst;
|
||||
taxi_axis_if #(
|
||||
.DATA_W(S_DATA_W),
|
||||
.KEEP_EN(S_KEEP_EN),
|
||||
.KEEP_W(S_KEEP_W),
|
||||
.STRB_EN(S_STRB_EN),
|
||||
.LAST_EN(1'b1),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis();
|
||||
|
||||
logic m_clk;
|
||||
logic m_rst;
|
||||
taxi_axis_if #(
|
||||
.DATA_W(M_DATA_W),
|
||||
.KEEP_EN(M_KEEP_EN),
|
||||
.KEEP_W(M_KEEP_W),
|
||||
.STRB_EN(M_STRB_EN),
|
||||
.LAST_EN(1'b1),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) m_axis();
|
||||
|
||||
logic s_pause_req;
|
||||
logic s_pause_ack;
|
||||
logic m_pause_req;
|
||||
logic m_pause_ack;
|
||||
|
||||
logic [$clog2(DEPTH):0] s_status_depth;
|
||||
logic [$clog2(DEPTH):0] s_status_depth_commit;
|
||||
logic s_status_overflow;
|
||||
logic s_status_bad_frame;
|
||||
logic s_status_good_frame;
|
||||
logic [$clog2(DEPTH):0] m_status_depth;
|
||||
logic [$clog2(DEPTH):0] m_status_depth_commit;
|
||||
logic m_status_overflow;
|
||||
logic m_status_bad_frame;
|
||||
logic m_status_good_frame;
|
||||
|
||||
taxi_axis_async_fifo_adapter #(
|
||||
.DEPTH(DEPTH),
|
||||
.RAM_PIPELINE(RAM_PIPELINE),
|
||||
.OUTPUT_FIFO_EN(OUTPUT_FIFO_EN),
|
||||
.FRAME_FIFO(FRAME_FIFO),
|
||||
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
|
||||
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
|
||||
.DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME),
|
||||
.DROP_BAD_FRAME(DROP_BAD_FRAME),
|
||||
.DROP_WHEN_FULL(DROP_WHEN_FULL),
|
||||
.MARK_WHEN_FULL(MARK_WHEN_FULL),
|
||||
.PAUSE_EN(PAUSE_EN),
|
||||
.FRAME_PAUSE(FRAME_PAUSE)
|
||||
)
|
||||
uut (
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_clk(s_clk),
|
||||
.s_rst(s_rst),
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_clk(m_clk),
|
||||
.m_rst(m_rst),
|
||||
.m_axis(m_axis),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.s_pause_req(s_pause_req),
|
||||
.s_pause_ack(s_pause_ack),
|
||||
.m_pause_req(m_pause_req),
|
||||
.m_pause_ack(m_pause_ack),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.s_status_depth(s_status_depth),
|
||||
.s_status_depth_commit(s_status_depth_commit),
|
||||
.s_status_overflow(s_status_overflow),
|
||||
.s_status_bad_frame(s_status_bad_frame),
|
||||
.s_status_good_frame(s_status_good_frame),
|
||||
.m_status_depth(m_status_depth),
|
||||
.m_status_depth_commit(m_status_depth_commit),
|
||||
.m_status_overflow(m_status_overflow),
|
||||
.m_status_bad_frame(m_status_bad_frame),
|
||||
.m_status_good_frame(m_status_good_frame)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
62
src/axis/tb/taxi_axis_broadcast/Makefile
Normal file
62
src/axis/tb/taxi_axis_broadcast/Makefile
Normal file
@@ -0,0 +1,62 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_broadcast
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_M_COUNT := 4
|
||||
export PARAM_DATA_W := 8
|
||||
export PARAM_KEEP_EN := $(shell expr $(PARAM_DATA_W) \> 8 )
|
||||
export PARAM_KEEP_W := $(shell expr \( $(PARAM_DATA_W) + 7 \) / 8 )
|
||||
export PARAM_STRB_EN := 0
|
||||
export PARAM_LAST_EN := 1
|
||||
export PARAM_ID_EN := 1
|
||||
export PARAM_ID_W := 8
|
||||
export PARAM_DEST_EN := 1
|
||||
export PARAM_DEST_W := 8
|
||||
export PARAM_USER_EN := 1
|
||||
export PARAM_USER_W := 1
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
190
src/axis/tb/taxi_axis_broadcast/test_taxi_axis_broadcast.py
Normal file
190
src/axis/tb/taxi_axis_broadcast/test_taxi_axis_broadcast.py
Normal file
@@ -0,0 +1,190 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
|
||||
self.sink = [AxiStreamSink(AxiStreamBus.from_entity(bus), dut.clk, dut.rst) for bus in dut.m_axis]
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
for sink in self.sink:
|
||||
sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
for sink in tb.sink:
|
||||
rx_frame = await sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
for sink in tb.sink:
|
||||
assert sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = len(cocotb.top.s_axis.tdata)
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32])
|
||||
@pytest.mark.parametrize("m_count", range(1, 4))
|
||||
def test_taxi_axis_broadcast(request, m_count, data_w):
|
||||
dut = "taxi_axis_broadcast"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_axis_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['M_COUNT'] = m_count
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
|
||||
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
|
||||
parameters['STRB_EN'] = 0
|
||||
parameters['LAST_EN'] = 1
|
||||
parameters['ID_EN'] = 1
|
||||
parameters['ID_W'] = 8
|
||||
parameters['DEST_EN'] = 1
|
||||
parameters['DEST_W'] = 8
|
||||
parameters['USER_EN'] = 1
|
||||
parameters['USER_W'] = 1
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
74
src/axis/tb/taxi_axis_broadcast/test_taxi_axis_broadcast.sv
Normal file
74
src/axis/tb/taxi_axis_broadcast/test_taxi_axis_broadcast.sv
Normal file
@@ -0,0 +1,74 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream broadcaster testbench
|
||||
*/
|
||||
module test_taxi_axis_broadcast #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter M_COUNT = 4,
|
||||
parameter DATA_W = 8,
|
||||
parameter logic KEEP_EN = (DATA_W>8),
|
||||
parameter KEEP_W = ((DATA_W+7)/8),
|
||||
parameter logic STRB_EN = 1'b0,
|
||||
parameter logic LAST_EN = 1'b1,
|
||||
parameter logic ID_EN = 1'b0,
|
||||
parameter ID_W = 8,
|
||||
parameter logic DEST_EN = 1'b0,
|
||||
parameter DEST_W = 8,
|
||||
parameter logic USER_EN = 1'b1,
|
||||
parameter USER_W = 1
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(STRB_EN),
|
||||
.LAST_EN(LAST_EN),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis(), m_axis[M_COUNT]();
|
||||
|
||||
taxi_axis_broadcast #(
|
||||
.M_COUNT(M_COUNT)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
51
src/axis/tb/taxi_axis_cobs_decode/Makefile
Normal file
51
src/axis/tb/taxi_axis_cobs_decode/Makefile
Normal file
@@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_cobs_decode
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
#export PARAM_APPEND_ZERO := 0
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
243
src/axis/tb/taxi_axis_cobs_decode/test_taxi_axis_cobs_decode.py
Normal file
243
src/axis/tb/taxi_axis_cobs_decode/test_taxi_axis_cobs_decode.py
Normal file
@@ -0,0 +1,243 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
def cobs_encode(block):
|
||||
block = bytearray(block)
|
||||
enc = bytearray()
|
||||
|
||||
seg = bytearray()
|
||||
code = 1
|
||||
|
||||
new_data = True
|
||||
|
||||
for b in block:
|
||||
if b == 0:
|
||||
enc.append(code)
|
||||
enc.extend(seg)
|
||||
code = 1
|
||||
seg = bytearray()
|
||||
new_data = True
|
||||
else:
|
||||
code += 1
|
||||
seg.append(b)
|
||||
new_data = True
|
||||
if code == 255:
|
||||
enc.append(code)
|
||||
enc.extend(seg)
|
||||
code = 1
|
||||
seg = bytearray()
|
||||
new_data = False
|
||||
|
||||
if new_data:
|
||||
enc.append(code)
|
||||
enc.extend(seg)
|
||||
|
||||
return bytes(enc)
|
||||
|
||||
|
||||
def cobs_decode(block):
|
||||
block = bytearray(block)
|
||||
dec = bytearray()
|
||||
|
||||
code = 0
|
||||
|
||||
i = 0
|
||||
|
||||
if 0 in block:
|
||||
return None
|
||||
|
||||
while i < len(block):
|
||||
code = block[i]
|
||||
i += 1
|
||||
if i+code-1 > len(block):
|
||||
return None
|
||||
dec.extend(block[i:i+code-1])
|
||||
i += code-1
|
||||
if code < 255 and i < len(block):
|
||||
dec.append(0)
|
||||
|
||||
return bytes(dec)
|
||||
|
||||
|
||||
def prbs31(state=0x7fffffff):
|
||||
while True:
|
||||
for i in range(8):
|
||||
if bool(state & 0x08000000) ^ bool(state & 0x40000000):
|
||||
state = ((state & 0x3fffffff) << 1) | 1
|
||||
else:
|
||||
state = (state & 0x3fffffff) << 1
|
||||
yield state & 0xff
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = [payload_data(x) for x in payload_lengths()]
|
||||
|
||||
for test_data in test_frames:
|
||||
enc = cobs_encode(test_data)
|
||||
test_frame = AxiStreamFrame(enc)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for test_data in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
return list(range(1, 33))+list(range(253, 259))+[512]+[1]*64
|
||||
|
||||
|
||||
def zero_payload(length):
|
||||
return bytearray(length)
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
def nonzero_incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(1, 256)), length))
|
||||
|
||||
|
||||
def nonzero_incrementing_payload_zero_framed(length):
|
||||
return bytearray([0]+list(itertools.islice(itertools.cycle(range(1, 256)), length))+[0])
|
||||
|
||||
|
||||
def prbs_payload(length):
|
||||
gen = prbs31()
|
||||
return bytearray([next(gen) for x in range(length)])
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [zero_payload, nonzero_incrementing_payload, nonzero_incrementing_payload_zero_framed, prbs_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
def test_taxi_axis_cobs_decode(request):
|
||||
dut = "taxi_axis_cobs_decode"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_axis_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
@@ -0,0 +1,48 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream COBS decoder testbench
|
||||
*/
|
||||
module test_taxi_axis_cobs_decode();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(8),
|
||||
.LAST_EN(1),
|
||||
.USER_EN(1),
|
||||
.USER_W(1)
|
||||
) s_axis(), m_axis();
|
||||
|
||||
taxi_axis_cobs_decode
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
50
src/axis/tb/taxi_axis_cobs_encode/Makefile
Normal file
50
src/axis/tb/taxi_axis_cobs_encode/Makefile
Normal file
@@ -0,0 +1,50 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_cobs_encode
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_APPEND_ZERO := 0
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
252
src/axis/tb/taxi_axis_cobs_encode/test_taxi_axis_cobs_encode.py
Normal file
252
src/axis/tb/taxi_axis_cobs_encode/test_taxi_axis_cobs_encode.py
Normal file
@@ -0,0 +1,252 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
def cobs_encode(block):
|
||||
block = bytearray(block)
|
||||
enc = bytearray()
|
||||
|
||||
seg = bytearray()
|
||||
code = 1
|
||||
|
||||
new_data = True
|
||||
|
||||
for b in block:
|
||||
if b == 0:
|
||||
enc.append(code)
|
||||
enc.extend(seg)
|
||||
code = 1
|
||||
seg = bytearray()
|
||||
new_data = True
|
||||
else:
|
||||
code += 1
|
||||
seg.append(b)
|
||||
new_data = True
|
||||
if code == 255:
|
||||
enc.append(code)
|
||||
enc.extend(seg)
|
||||
code = 1
|
||||
seg = bytearray()
|
||||
new_data = False
|
||||
|
||||
if new_data:
|
||||
enc.append(code)
|
||||
enc.extend(seg)
|
||||
|
||||
return bytes(enc)
|
||||
|
||||
|
||||
def cobs_decode(block):
|
||||
block = bytearray(block)
|
||||
dec = bytearray()
|
||||
|
||||
code = 0
|
||||
|
||||
i = 0
|
||||
|
||||
if 0 in block:
|
||||
return None
|
||||
|
||||
while i < len(block):
|
||||
code = block[i]
|
||||
i += 1
|
||||
if i+code-1 > len(block):
|
||||
return None
|
||||
dec.extend(block[i:i+code-1])
|
||||
i += code-1
|
||||
if code < 255 and i < len(block):
|
||||
dec.append(0)
|
||||
|
||||
return bytes(dec)
|
||||
|
||||
|
||||
def prbs31(state=0x7fffffff):
|
||||
while True:
|
||||
for i in range(8):
|
||||
if bool(state & 0x08000000) ^ bool(state & 0x40000000):
|
||||
state = ((state & 0x3fffffff) << 1) | 1
|
||||
else:
|
||||
state = (state & 0x3fffffff) << 1
|
||||
yield state & 0xff
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
append_zero = int(os.getenv("PARAM_APPEND_ZERO"))
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = [payload_data(x) for x in payload_lengths()]
|
||||
|
||||
for test_data in test_frames:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for test_data in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if append_zero:
|
||||
assert rx_frame.tdata == cobs_encode(test_data)+b'\x00'
|
||||
assert cobs_decode(rx_frame.tdata[:-1]) == test_data
|
||||
else:
|
||||
assert rx_frame.tdata == cobs_encode(test_data)
|
||||
assert cobs_decode(rx_frame.tdata) == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
return list(range(1, 33))+list(range(253, 259))+[512]+[1]*64
|
||||
|
||||
|
||||
def zero_payload(length):
|
||||
return bytearray(length)
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
def nonzero_incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(1, 256)), length))
|
||||
|
||||
|
||||
def nonzero_incrementing_payload_zero_framed(length):
|
||||
return bytearray([0]+list(itertools.islice(itertools.cycle(range(1, 256)), length))+[0])
|
||||
|
||||
|
||||
def prbs_payload(length):
|
||||
gen = prbs31()
|
||||
return bytearray([next(gen) for x in range(length)])
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [zero_payload, nonzero_incrementing_payload, nonzero_incrementing_payload_zero_framed, prbs_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("append_zero", [0, 1])
|
||||
def test_taxi_axis_cobs_encode(request, append_zero):
|
||||
dut = "taxi_axis_cobs_encode"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['APPEND_ZERO'] = append_zero
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
@@ -0,0 +1,56 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream COBS encoder testbench
|
||||
*/
|
||||
module test_taxi_axis_cobs_encode #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter logic APPEND_ZERO = 1'b1
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(8),
|
||||
.LAST_EN(1),
|
||||
.USER_EN(1),
|
||||
.USER_W(1)
|
||||
) s_axis(), m_axis();
|
||||
|
||||
taxi_axis_cobs_encode #(
|
||||
.APPEND_ZERO(APPEND_ZERO)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
73
src/axis/tb/taxi_axis_fifo/Makefile
Normal file
73
src/axis/tb/taxi_axis_fifo/Makefile
Normal file
@@ -0,0 +1,73 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_fifo
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_W := 8
|
||||
export PARAM_KEEP_EN := $(shell echo $$(( $(PARAM_DATA_W) > 8 )))
|
||||
export PARAM_KEEP_W := $(shell echo $$(( ( $(PARAM_DATA_W) + 7 ) / 8 )))
|
||||
export PARAM_STRB_EN := 0
|
||||
export PARAM_DEPTH := $(shell echo $$(( 1024 * $(PARAM_KEEP_W) )))
|
||||
export PARAM_LAST_EN := 1
|
||||
export PARAM_ID_EN := 1
|
||||
export PARAM_ID_W := 8
|
||||
export PARAM_DEST_EN := 1
|
||||
export PARAM_DEST_W := 8
|
||||
export PARAM_USER_EN := 1
|
||||
export PARAM_USER_W := 1
|
||||
export PARAM_RAM_PIPELINE := 1
|
||||
export PARAM_OUTPUT_FIFO_EN := 0
|
||||
export PARAM_FRAME_FIFO := 1
|
||||
export PARAM_USER_BAD_FRAME_VALUE := 1
|
||||
export PARAM_USER_BAD_FRAME_MASK := 1
|
||||
export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
|
||||
export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
|
||||
export PARAM_DROP_WHEN_FULL := 0
|
||||
export PARAM_MARK_WHEN_FULL := 0
|
||||
export PARAM_PAUSE_EN := 1
|
||||
export PARAM_FRAME_PAUSE := 1
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
514
src/axis/tb/taxi_axis_fifo/test_taxi_axis_fifo.py
Normal file
514
src/axis/tb/taxi_axis_fifo/test_taxi_axis_fifo.py
Normal file
@@ -0,0 +1,514 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
|
||||
|
||||
dut.pause_req.setimmediatevalue(0)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_tuser_assert(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data, tuser=1)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
if dut.DROP_BAD_FRAME.value:
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
else:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_pause(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.source.byte_lanes
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 16*byte_lanes))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
|
||||
for k in range(16):
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(60):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
dut.pause_req.value = 1
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
dut.pause_req.value = 0
|
||||
|
||||
for k in range(16):
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_overflow(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
depth = int(dut.DEPTH.value)
|
||||
byte_lanes = tb.source.byte_lanes
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
size = (16*byte_lanes)
|
||||
count = depth*2 // size
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), size))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
for k in range(count):
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range((depth//byte_lanes)*3):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value:
|
||||
assert tb.source.idle()
|
||||
else:
|
||||
assert not tb.source.idle()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value:
|
||||
for k in range((depth//byte_lanes)*3):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
rx_count = 0
|
||||
|
||||
while not tb.sink.empty():
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if dut.MARK_WHEN_FULL.value and rx_frame.tuser:
|
||||
continue
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
rx_count += 1
|
||||
|
||||
assert rx_count < count
|
||||
|
||||
else:
|
||||
for k in range(count):
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_oversize(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
depth = int(dut.DEPTH.value)
|
||||
byte_lanes = tb.source.byte_lanes
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), depth*2))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range((depth//byte_lanes)*2):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
if dut.DROP_OVERSIZE_FRAME.value:
|
||||
for k in range((depth//byte_lanes)*2):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
else:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if dut.MARK_WHEN_FULL.value:
|
||||
assert rx_frame.tuser
|
||||
else:
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.source.byte_lanes
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for k in range(512):
|
||||
length = random.randint(1, byte_lanes*16)
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value:
|
||||
cycles = 0
|
||||
while cycles < 100:
|
||||
cycles += 1
|
||||
if not tb.source.idle() or dut.s_axis.tvalid.value.integer or dut.m_axis.tvalid.value.integer or dut.status_depth.value.integer:
|
||||
cycles = 0
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
while not tb.sink.empty():
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if dut.MARK_WHEN_FULL.value and rx_frame.tuser:
|
||||
continue
|
||||
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert len(test_frames) > 0
|
||||
|
||||
while True:
|
||||
test_frame = test_frames.pop(0)
|
||||
if rx_frame.tid == test_frame.tid and rx_frame.tdest == test_frame.tdest and rx_frame.tdata == test_frame.tdata:
|
||||
break
|
||||
|
||||
assert len(test_frames) < 512
|
||||
|
||||
else:
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = len(cocotb.top.m_axis.tdata)
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [
|
||||
run_test_tuser_assert,
|
||||
run_test_init_sink_pause,
|
||||
run_test_init_sink_pause_reset,
|
||||
run_test_pause,
|
||||
run_test_overflow,
|
||||
run_test_oversize
|
||||
]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame",
|
||||
"drop_when_full", "mark_when_full"),
|
||||
[(0, 0, 0, 0, 0), (1, 0, 0, 0, 0), (1, 1, 0, 0, 0), (1, 1, 1, 0, 0),
|
||||
(1, 1, 1, 1, 0), (0, 0, 0, 0, 1)])
|
||||
@pytest.mark.parametrize(("ram_pipeline", "output_fifo"),
|
||||
[(0, 0), (1, 0), (4, 0), (0, 1), (1, 1), (4, 1)])
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32, 64])
|
||||
def test_taxi_axis_fifo(request, data_w, ram_pipeline, output_fifo,
|
||||
frame_fifo, drop_oversize_frame, drop_bad_frame,
|
||||
drop_when_full, mark_when_full):
|
||||
|
||||
dut = "taxi_axis_fifo"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_axis_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
|
||||
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
|
||||
parameters['STRB_EN'] = 0
|
||||
parameters['DEPTH'] = 1024 * parameters['KEEP_W']
|
||||
parameters['LAST_EN'] = 1
|
||||
parameters['ID_EN'] = 1
|
||||
parameters['ID_W'] = 8
|
||||
parameters['DEST_EN'] = 1
|
||||
parameters['DEST_W'] = 8
|
||||
parameters['USER_EN'] = 1
|
||||
parameters['USER_W'] = 1
|
||||
parameters['RAM_PIPELINE'] = ram_pipeline
|
||||
parameters['OUTPUT_FIFO_EN'] = output_fifo
|
||||
parameters['FRAME_FIFO'] = frame_fifo
|
||||
parameters['USER_BAD_FRAME_VALUE'] = 1
|
||||
parameters['USER_BAD_FRAME_MASK'] = 1
|
||||
parameters['DROP_OVERSIZE_FRAME'] = drop_oversize_frame
|
||||
parameters['DROP_BAD_FRAME'] = drop_bad_frame
|
||||
parameters['DROP_WHEN_FULL'] = drop_when_full
|
||||
parameters['MARK_WHEN_FULL'] = mark_when_full
|
||||
parameters['PAUSE_EN'] = 1
|
||||
parameters['FRAME_PAUSE'] = 1
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
120
src/axis/tb/taxi_axis_fifo/test_taxi_axis_fifo.sv
Normal file
120
src/axis/tb/taxi_axis_fifo/test_taxi_axis_fifo.sv
Normal file
@@ -0,0 +1,120 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream FIFO testbench
|
||||
*/
|
||||
module test_taxi_axis_fifo #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DEPTH = 4096,
|
||||
parameter DATA_W = 8,
|
||||
parameter logic KEEP_EN = (DATA_W>8),
|
||||
parameter KEEP_W = ((DATA_W+7)/8),
|
||||
parameter logic STRB_EN = 1'b0,
|
||||
parameter logic LAST_EN = 1'b1,
|
||||
parameter logic ID_EN = 1'b0,
|
||||
parameter ID_W = 8,
|
||||
parameter logic DEST_EN = 1'b0,
|
||||
parameter DEST_W = 8,
|
||||
parameter logic USER_EN = 1'b1,
|
||||
parameter USER_W = 1,
|
||||
parameter RAM_PIPELINE = 1,
|
||||
parameter logic OUTPUT_FIFO_EN = 1'b0,
|
||||
parameter logic FRAME_FIFO = 1'b0,
|
||||
parameter logic [USER_W-1:0] USER_BAD_FRAME_VALUE = 1'b1,
|
||||
parameter logic [USER_W-1:0] USER_BAD_FRAME_MASK = 1'b1,
|
||||
parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
|
||||
parameter logic DROP_BAD_FRAME = 1'b0,
|
||||
parameter logic DROP_WHEN_FULL = 1'b0,
|
||||
parameter logic MARK_WHEN_FULL = 1'b0,
|
||||
parameter logic PAUSE_EN = 1'b0,
|
||||
parameter logic FRAME_PAUSE = FRAME_FIFO
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(STRB_EN),
|
||||
.LAST_EN(LAST_EN),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis(), m_axis();
|
||||
|
||||
logic pause_req;
|
||||
logic pause_ack;
|
||||
|
||||
logic [$clog2(DEPTH):0] status_depth;
|
||||
logic [$clog2(DEPTH):0] status_depth_commit;
|
||||
logic status_overflow;
|
||||
logic status_bad_frame;
|
||||
logic status_good_frame;
|
||||
|
||||
taxi_axis_fifo #(
|
||||
.DEPTH(DEPTH),
|
||||
.RAM_PIPELINE(RAM_PIPELINE),
|
||||
.OUTPUT_FIFO_EN(OUTPUT_FIFO_EN),
|
||||
.FRAME_FIFO(FRAME_FIFO),
|
||||
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
|
||||
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
|
||||
.DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME),
|
||||
.DROP_BAD_FRAME(DROP_BAD_FRAME),
|
||||
.DROP_WHEN_FULL(DROP_WHEN_FULL),
|
||||
.MARK_WHEN_FULL(MARK_WHEN_FULL),
|
||||
.PAUSE_EN(PAUSE_EN),
|
||||
.FRAME_PAUSE(FRAME_PAUSE)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.pause_req(pause_req),
|
||||
.pause_ack(pause_ack),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.status_depth(status_depth),
|
||||
.status_depth_commit(status_depth_commit),
|
||||
.status_overflow(status_overflow),
|
||||
.status_bad_frame(status_bad_frame),
|
||||
.status_good_frame(status_good_frame)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
75
src/axis/tb/taxi_axis_fifo_adapter/Makefile
Normal file
75
src/axis/tb/taxi_axis_fifo_adapter/Makefile
Normal file
@@ -0,0 +1,75 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_fifo_adapter
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_S_DATA_W := 8
|
||||
export PARAM_S_KEEP_EN := $(shell echo $$(( $(PARAM_S_DATA_W) > 8 )))
|
||||
export PARAM_S_KEEP_W := $(shell echo $$(( ( $(PARAM_S_DATA_W) + 7 ) / 8 )))
|
||||
export PARAM_S_STRB_EN := 0
|
||||
export PARAM_M_DATA_W := 8
|
||||
export PARAM_M_KEEP_EN := $(shell echo $$(( $(PARAM_M_DATA_W) > 8 )))
|
||||
export PARAM_M_KEEP_W := $(shell echo $$(( ( $(PARAM_M_DATA_W) + 7 ) / 8 )))
|
||||
export PARAM_M_STRB_EN := $(PARAM_S_STRB_EN)
|
||||
export PARAM_DEPTH := $(shell echo $$(( 1024 * ($(PARAM_S_KEEP_W) > $(PARAM_M_KEEP_W) ? $(PARAM_S_KEEP_W) : $(PARAM_M_KEEP_W)) )))
|
||||
export PARAM_ID_EN := 1
|
||||
export PARAM_ID_W := 8
|
||||
export PARAM_DEST_EN := 1
|
||||
export PARAM_DEST_W := 8
|
||||
export PARAM_USER_EN := 1
|
||||
export PARAM_USER_W := 1
|
||||
export PARAM_RAM_PIPELINE := 1
|
||||
export PARAM_OUTPUT_FIFO_EN := 0
|
||||
export PARAM_FRAME_FIFO := 1
|
||||
export PARAM_USER_BAD_FRAME_VALUE := 1
|
||||
export PARAM_USER_BAD_FRAME_MASK := 1
|
||||
export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
|
||||
export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
|
||||
export PARAM_DROP_WHEN_FULL := 0
|
||||
export PARAM_MARK_WHEN_FULL := 0
|
||||
export PARAM_PAUSE_EN := 1
|
||||
export PARAM_FRAME_PAUSE := 1
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
@@ -0,0 +1,513 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
|
||||
|
||||
dut.pause_req.setimmediatevalue(0)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_tuser_assert(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data, tuser=1)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
if int(dut.DROP_BAD_FRAME.value):
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
else:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_pause(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = max(tb.source.byte_lanes, tb.sink.byte_lanes)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 16*byte_lanes))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
|
||||
for k in range(16):
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(60):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
dut.pause_req.value = 1
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
assert tb.sink.idle()
|
||||
|
||||
dut.pause_req.value = 0
|
||||
|
||||
for k in range(16):
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_overflow(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
depth = int(dut.DEPTH.value)
|
||||
byte_lanes = min(tb.source.byte_lanes, tb.sink.byte_lanes)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
size = (16*byte_lanes)
|
||||
count = depth*2 // size
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), size))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
for k in range(count):
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range((depth//byte_lanes)*3):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
|
||||
assert tb.source.idle()
|
||||
else:
|
||||
assert not tb.source.idle()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
|
||||
for k in range((depth//byte_lanes)*3):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
rx_count = 0
|
||||
|
||||
while not tb.sink.empty():
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if int(dut.MARK_WHEN_FULL.value) and rx_frame.tuser:
|
||||
continue
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
rx_count += 1
|
||||
|
||||
assert rx_count < count
|
||||
|
||||
else:
|
||||
for k in range(count):
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_oversize(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
depth = int(dut.DEPTH.value)
|
||||
byte_lanes = min(tb.source.byte_lanes, tb.sink.byte_lanes)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), depth*2))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range((depth//byte_lanes)*2):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
if dut.DROP_OVERSIZE_FRAME.value:
|
||||
for k in range((depth//byte_lanes)*2):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
else:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if dut.MARK_WHEN_FULL.value:
|
||||
assert rx_frame.tuser
|
||||
else:
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = max(tb.source.byte_lanes, tb.sink.byte_lanes)
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for k in range(512):
|
||||
length = random.randint(1, byte_lanes*16)
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
|
||||
cycles = 0
|
||||
while cycles < 100:
|
||||
cycles += 1
|
||||
if not tb.source.idle() or int(dut.s_axis.tvalid.value) or int(dut.m_axis.tvalid.value) or int(dut.status_depth.value):
|
||||
cycles = 0
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
while not tb.sink.empty():
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
if int(dut.MARK_WHEN_FULL.value) and rx_frame.tuser:
|
||||
continue
|
||||
|
||||
assert not rx_frame.tuser
|
||||
|
||||
while True:
|
||||
test_frame = test_frames.pop(0)
|
||||
if rx_frame.tid == test_frame.tid and rx_frame.tdest == test_frame.tdest and rx_frame.tdata == test_frame.tdata:
|
||||
break
|
||||
|
||||
assert len(test_frames) < 512
|
||||
|
||||
else:
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = max(len(cocotb.top.m_axis.tdata), len(cocotb.top.s_axis.tdata))
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [
|
||||
run_test_tuser_assert,
|
||||
run_test_init_sink_pause,
|
||||
run_test_init_sink_pause_reset,
|
||||
run_test_pause,
|
||||
run_test_overflow,
|
||||
run_test_oversize
|
||||
]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame",
|
||||
"drop_when_full", "mark_when_full"),
|
||||
[(0, 0, 0, 0, 0), (1, 0, 0, 0, 0), (1, 1, 0, 0, 0), (1, 1, 1, 0, 0),
|
||||
(1, 1, 1, 1, 0), (0, 0, 0, 0, 1)])
|
||||
@pytest.mark.parametrize("m_data_width", [8, 16, 32])
|
||||
@pytest.mark.parametrize("s_data_width", [8, 16, 32])
|
||||
def test_taxi_axis_fifo_adapter(request, s_data_width, m_data_width,
|
||||
frame_fifo, drop_oversize_frame, drop_bad_frame,
|
||||
drop_when_full, mark_when_full):
|
||||
|
||||
dut = "taxi_axis_fifo_adapter"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['S_DATA_W'] = s_data_width
|
||||
parameters['S_KEEP_EN'] = int(parameters['S_DATA_W'] > 8)
|
||||
parameters['S_KEEP_W'] = (parameters['S_DATA_W'] + 7) // 8
|
||||
parameters['S_STRB_EN'] = 0
|
||||
parameters['M_DATA_W'] = m_data_width
|
||||
parameters['M_KEEP_EN'] = int(parameters['M_DATA_W'] > 8)
|
||||
parameters['M_KEEP_W'] = (parameters['M_DATA_W'] + 7) // 8
|
||||
parameters['M_STRB_EN'] = parameters['S_STRB_EN']
|
||||
parameters['DEPTH'] = 1024 * max(parameters['S_KEEP_W'], parameters['M_KEEP_W'])
|
||||
parameters['ID_EN'] = 1
|
||||
parameters['ID_W'] = 8
|
||||
parameters['DEST_EN'] = 1
|
||||
parameters['DEST_W'] = 8
|
||||
parameters['USER_EN'] = 1
|
||||
parameters['USER_W'] = 1
|
||||
parameters['RAM_PIPELINE'] = 1
|
||||
parameters['OUTPUT_FIFO_EN'] = 0
|
||||
parameters['FRAME_FIFO'] = frame_fifo
|
||||
parameters['USER_BAD_FRAME_VALUE'] = 1
|
||||
parameters['USER_BAD_FRAME_MASK'] = 1
|
||||
parameters['DROP_OVERSIZE_FRAME'] = drop_oversize_frame
|
||||
parameters['DROP_BAD_FRAME'] = drop_bad_frame
|
||||
parameters['DROP_WHEN_FULL'] = drop_when_full
|
||||
parameters['MARK_WHEN_FULL'] = mark_when_full
|
||||
parameters['PAUSE_EN'] = 1
|
||||
parameters['FRAME_PAUSE'] = 1
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
@@ -0,0 +1,137 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream FIFO with width converter testbench
|
||||
*/
|
||||
module test_taxi_axis_fifo_adapter #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DEPTH = 4096,
|
||||
parameter S_DATA_W = 8,
|
||||
parameter logic S_KEEP_EN = (S_DATA_W>8),
|
||||
parameter S_KEEP_W = ((S_DATA_W+7)/8),
|
||||
parameter logic S_STRB_EN = 0,
|
||||
parameter M_DATA_W = 8,
|
||||
parameter logic M_KEEP_EN = (M_DATA_W>8),
|
||||
parameter M_KEEP_W = ((M_DATA_W+7)/8),
|
||||
parameter logic M_STRB_EN = 0,
|
||||
parameter logic ID_EN = 1'b0,
|
||||
parameter ID_W = 8,
|
||||
parameter logic DEST_EN = 1'b0,
|
||||
parameter DEST_W = 8,
|
||||
parameter logic USER_EN = 1'b1,
|
||||
parameter USER_W = 1,
|
||||
parameter RAM_PIPELINE = 1,
|
||||
parameter logic OUTPUT_FIFO_EN = 1'b0,
|
||||
parameter logic FRAME_FIFO = 1'b0,
|
||||
parameter logic [USER_W-1:0] USER_BAD_FRAME_VALUE = 1'b1,
|
||||
parameter logic [USER_W-1:0] USER_BAD_FRAME_MASK = 1'b1,
|
||||
parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
|
||||
parameter logic DROP_BAD_FRAME = 1'b0,
|
||||
parameter logic DROP_WHEN_FULL = 1'b0,
|
||||
parameter logic MARK_WHEN_FULL = 1'b0,
|
||||
parameter logic PAUSE_EN = 1'b0,
|
||||
parameter logic FRAME_PAUSE = FRAME_FIFO
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(S_DATA_W),
|
||||
.KEEP_EN(S_KEEP_EN),
|
||||
.KEEP_W(S_KEEP_W),
|
||||
.STRB_EN(S_STRB_EN),
|
||||
.LAST_EN(1'b1),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis();
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(M_DATA_W),
|
||||
.KEEP_EN(M_KEEP_EN),
|
||||
.KEEP_W(M_KEEP_W),
|
||||
.STRB_EN(M_STRB_EN),
|
||||
.LAST_EN(1'b1),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) m_axis();
|
||||
|
||||
logic pause_req;
|
||||
logic pause_ack;
|
||||
|
||||
logic [$clog2(DEPTH):0] status_depth;
|
||||
logic [$clog2(DEPTH):0] status_depth_commit;
|
||||
logic status_overflow;
|
||||
logic status_bad_frame;
|
||||
logic status_good_frame;
|
||||
|
||||
taxi_axis_fifo_adapter #(
|
||||
.DEPTH(DEPTH),
|
||||
.RAM_PIPELINE(RAM_PIPELINE),
|
||||
.OUTPUT_FIFO_EN(OUTPUT_FIFO_EN),
|
||||
.FRAME_FIFO(FRAME_FIFO),
|
||||
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
|
||||
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
|
||||
.DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME),
|
||||
.DROP_BAD_FRAME(DROP_BAD_FRAME),
|
||||
.DROP_WHEN_FULL(DROP_WHEN_FULL),
|
||||
.MARK_WHEN_FULL(MARK_WHEN_FULL),
|
||||
.PAUSE_EN(PAUSE_EN),
|
||||
.FRAME_PAUSE(FRAME_PAUSE)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis),
|
||||
|
||||
/*
|
||||
* Pause
|
||||
*/
|
||||
.pause_req(pause_req),
|
||||
.pause_ack(pause_ack),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.status_depth(status_depth),
|
||||
.status_depth_commit(status_depth_commit),
|
||||
.status_overflow(status_overflow),
|
||||
.status_bad_frame(status_bad_frame),
|
||||
.status_good_frame(status_good_frame)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
62
src/axis/tb/taxi_axis_mux/Makefile
Normal file
62
src/axis/tb/taxi_axis_mux/Makefile
Normal file
@@ -0,0 +1,62 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_mux
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_S_COUNT := 4
|
||||
export PARAM_DATA_W := 8
|
||||
export PARAM_KEEP_EN := $(shell expr $(PARAM_DATA_W) \> 8 )
|
||||
export PARAM_KEEP_W := $(shell expr \( $(PARAM_DATA_W) + 7 \) / 8 )
|
||||
export PARAM_STRB_EN := 0
|
||||
export PARAM_LAST_EN := 1
|
||||
export PARAM_ID_EN := 1
|
||||
export PARAM_ID_W := 8
|
||||
export PARAM_DEST_EN := 1
|
||||
export PARAM_DEST_W := 8
|
||||
export PARAM_USER_EN := 1
|
||||
export PARAM_USER_W := 1
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
226
src/axis/tb/taxi_axis_mux/test_taxi_axis_mux.py
Normal file
226
src/axis/tb/taxi_axis_mux/test_taxi_axis_mux.py
Normal file
@@ -0,0 +1,226 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = [AxiStreamSource(AxiStreamBus.from_entity(bus), dut.clk, dut.rst) for bus in dut.s_axis]
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
|
||||
|
||||
dut.enable.setimmediatevalue(0)
|
||||
dut.select.setimmediatevalue(0)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
for source in self.source:
|
||||
source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None, port=0):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_count = 2**len(tb.source[port].bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
dut.enable.setimmediatevalue(1)
|
||||
dut.select.setimmediatevalue(port)
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source[port].send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_tuser_assert(dut, port=0):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
dut.enable.setimmediatevalue(1)
|
||||
dut.select.setimmediatevalue(port)
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data, tuser=1)
|
||||
await tb.source[port].send(test_frame)
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = len(cocotb.top.m_axis.tdata)
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
ports = len(cocotb.top.s_axis)
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.add_option("port", list(range(ports)))
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [run_test_tuser_assert]:
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("port", list(range(ports)))
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32])
|
||||
@pytest.mark.parametrize("s_count", [4])
|
||||
def test_taxi_axis_mux(request, s_count, data_w):
|
||||
dut = "taxi_axis_mux"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_axis_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['S_COUNT'] = s_count
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
|
||||
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
|
||||
parameters['STRB_EN'] = 0
|
||||
parameters['LAST_EN'] = 1
|
||||
parameters['ID_EN'] = 1
|
||||
parameters['ID_W'] = 8
|
||||
parameters['DEST_EN'] = 1
|
||||
parameters['DEST_W'] = 8
|
||||
parameters['USER_EN'] = 1
|
||||
parameters['USER_W'] = 1
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
83
src/axis/tb/taxi_axis_mux/test_taxi_axis_mux.sv
Normal file
83
src/axis/tb/taxi_axis_mux/test_taxi_axis_mux.sv
Normal file
@@ -0,0 +1,83 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream multiplexer testbench
|
||||
*/
|
||||
module test_taxi_axis_mux #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter S_COUNT = 4,
|
||||
parameter DATA_W = 8,
|
||||
parameter logic KEEP_EN = (DATA_W>8),
|
||||
parameter KEEP_W = ((DATA_W+7)/8),
|
||||
parameter logic STRB_EN = 1'b0,
|
||||
parameter logic LAST_EN = 1'b1,
|
||||
parameter logic ID_EN = 1'b0,
|
||||
parameter ID_W = 8,
|
||||
parameter logic DEST_EN = 1'b0,
|
||||
parameter DEST_W = 8,
|
||||
parameter logic USER_EN = 1'b1,
|
||||
parameter USER_W = 1
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(STRB_EN),
|
||||
.LAST_EN(LAST_EN),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis[S_COUNT](), m_axis();
|
||||
|
||||
logic enable;
|
||||
logic [$clog2(S_COUNT)-1:0] select;
|
||||
|
||||
taxi_axis_mux #(
|
||||
.S_COUNT(S_COUNT)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis),
|
||||
|
||||
/*
|
||||
* Control
|
||||
*/
|
||||
.enable(enable),
|
||||
.select(select)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
62
src/axis/tb/taxi_axis_pipeline_fifo/Makefile
Normal file
62
src/axis/tb/taxi_axis_pipeline_fifo/Makefile
Normal file
@@ -0,0 +1,62 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_pipeline_fifo
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_W := 8
|
||||
export PARAM_KEEP_EN := $(shell echo $$(( $(PARAM_DATA_W) > 8 )))
|
||||
export PARAM_KEEP_W := $(shell echo $$(( ( $(PARAM_DATA_W) + 7 ) / 8 )))
|
||||
export PARAM_STRB_EN := 0
|
||||
export PARAM_LAST_EN := 1
|
||||
export PARAM_ID_EN := 1
|
||||
export PARAM_ID_W := 8
|
||||
export PARAM_DEST_EN := 1
|
||||
export PARAM_DEST_W := 8
|
||||
export PARAM_USER_EN := 1
|
||||
export PARAM_USER_W := 1
|
||||
export PARAM_LENGTH := 2
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
@@ -0,0 +1,350 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_tuser_assert(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data, tuser=1)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_init_sink_pause_reset(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
for k in range(64):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_overflow(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.sink.pause = True
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 2048))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
for k in range(2048):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
tb.sink.pause = False
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.source.byte_lanes
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for k in range(128):
|
||||
length = random.randint(1, byte_lanes*16)
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = len(cocotb.top.m_axis.tdata)
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [
|
||||
run_test_tuser_assert,
|
||||
run_test_init_sink_pause,
|
||||
run_test_init_sink_pause_reset,
|
||||
run_test_overflow
|
||||
]:
|
||||
|
||||
factory = TestFactory(test)
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("data_w", [8, 16])
|
||||
@pytest.mark.parametrize("length", list(range(17)))
|
||||
def test_taxi_axis_pipeline_fifo(request, length, data_w):
|
||||
dut = "taxi_axis_pipeline_fifo"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_axis_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
|
||||
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
|
||||
parameters['STRB_EN'] = 0
|
||||
parameters['LAST_EN'] = 1
|
||||
parameters['ID_EN'] = 1
|
||||
parameters['ID_W'] = 8
|
||||
parameters['DEST_EN'] = 1
|
||||
parameters['DEST_W'] = 8
|
||||
parameters['USER_EN'] = 1
|
||||
parameters['USER_W'] = 1
|
||||
parameters['LENGTH'] = length
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
@@ -0,0 +1,74 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream pipeline FIFO testbench
|
||||
*/
|
||||
module test_taxi_axis_pipeline_fifo #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DATA_W = 8,
|
||||
parameter logic KEEP_EN = (DATA_W>8),
|
||||
parameter KEEP_W = ((DATA_W+7)/8),
|
||||
parameter logic STRB_EN = 1'b0,
|
||||
parameter logic LAST_EN = 1'b1,
|
||||
parameter logic ID_EN = 1'b0,
|
||||
parameter ID_W = 8,
|
||||
parameter logic DEST_EN = 1'b0,
|
||||
parameter DEST_W = 8,
|
||||
parameter logic USER_EN = 1'b1,
|
||||
parameter USER_W = 1,
|
||||
parameter LENGTH = 2
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(STRB_EN),
|
||||
.LAST_EN(LAST_EN),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis(), m_axis();
|
||||
|
||||
taxi_axis_pipeline_fifo #(
|
||||
.LENGTH(LENGTH)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
62
src/axis/tb/taxi_axis_pipeline_register/Makefile
Normal file
62
src/axis/tb/taxi_axis_pipeline_register/Makefile
Normal file
@@ -0,0 +1,62 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_pipeline_register
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_W := 8
|
||||
export PARAM_KEEP_EN := $(shell echo $$(( $(PARAM_DATA_W) > 8 )))
|
||||
export PARAM_KEEP_W := $(shell echo $$(( ( $(PARAM_DATA_W) + 7 ) / 8 )))
|
||||
export PARAM_STRB_EN := 0
|
||||
export PARAM_LAST_EN := 1
|
||||
export PARAM_ID_EN := 1
|
||||
export PARAM_ID_W := 8
|
||||
export PARAM_DEST_EN := 1
|
||||
export PARAM_DEST_W := 8
|
||||
export PARAM_USER_EN := 1
|
||||
export PARAM_USER_W := 1
|
||||
export PARAM_REG_TYPE := 2
|
||||
export PARAM_LENGTH := 2
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
@@ -0,0 +1,261 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_tuser_assert(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data, tuser=1)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.source.byte_lanes
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for k in range(128):
|
||||
length = random.randint(1, byte_lanes*16)
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = len(cocotb.top.m_axis.tdata)
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [run_test_tuser_assert]:
|
||||
factory = TestFactory(test)
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("reg_type", [0, 1, 2])
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32])
|
||||
@pytest.mark.parametrize("length", [0, 1, 2])
|
||||
def test_taxi_axis_pipeline_register(request, length, data_w, reg_type):
|
||||
dut = "taxi_axis_pipeline_register"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
|
||||
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
|
||||
parameters['STRB_EN'] = 0
|
||||
parameters['LAST_EN'] = 1
|
||||
parameters['ID_EN'] = 1
|
||||
parameters['ID_W'] = 8
|
||||
parameters['DEST_EN'] = 1
|
||||
parameters['DEST_W'] = 8
|
||||
parameters['USER_EN'] = 1
|
||||
parameters['USER_W'] = 1
|
||||
parameters['REG_TYPE'] = reg_type
|
||||
parameters['LENGTH'] = length
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
@@ -0,0 +1,76 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream pipeline register testbench
|
||||
*/
|
||||
module test_taxi_axis_pipeline_register #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DATA_W = 8,
|
||||
parameter logic KEEP_EN = (DATA_W>8),
|
||||
parameter KEEP_W = ((DATA_W+7)/8),
|
||||
parameter logic STRB_EN = 1'b0,
|
||||
parameter logic LAST_EN = 1'b1,
|
||||
parameter logic ID_EN = 1'b0,
|
||||
parameter ID_W = 8,
|
||||
parameter logic DEST_EN = 1'b0,
|
||||
parameter DEST_W = 8,
|
||||
parameter logic USER_EN = 1'b1,
|
||||
parameter USER_W = 1,
|
||||
parameter REG_TYPE = 2,
|
||||
parameter LENGTH = 2
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(STRB_EN),
|
||||
.LAST_EN(LAST_EN),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis(), m_axis();
|
||||
|
||||
taxi_axis_pipeline_register #(
|
||||
.REG_TYPE(REG_TYPE),
|
||||
.LENGTH(LENGTH)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
62
src/axis/tb/taxi_axis_register/Makefile
Normal file
62
src/axis/tb/taxi_axis_register/Makefile
Normal file
@@ -0,0 +1,62 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = taxi_axis_register
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/taxi_axis_if.sv
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_W := 8
|
||||
export PARAM_KEEP_EN := $(shell echo $$(( $(PARAM_DATA_W) > 8 )))
|
||||
export PARAM_KEEP_W := $(shell echo $$(( ( $(PARAM_DATA_W) + 7 ) / 8 )))
|
||||
export PARAM_STRB_EN := 0
|
||||
export PARAM_LAST_EN := 1
|
||||
export PARAM_ID_EN := 1
|
||||
export PARAM_ID_W := 8
|
||||
export PARAM_DEST_EN := 1
|
||||
export PARAM_DEST_W := 8
|
||||
export PARAM_USER_EN := 1
|
||||
export PARAM_USER_W := 1
|
||||
export PARAM_REG_TYPE := 2
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
260
src/axis/tb/taxi_axis_register/test_taxi_axis_register.py
Normal file
260
src/axis/tb/taxi_axis_register/test_taxi_axis_register.py
Normal file
@@ -0,0 +1,260 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2021-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
|
||||
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
self.source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
self.sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_tuser_assert(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data, tuser=1)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.source.byte_lanes
|
||||
id_count = 2**len(tb.source.bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for k in range(128):
|
||||
length = random.randint(1, byte_lanes*16)
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = cur_id
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source.send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink.recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert tb.sink.empty()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = len(cocotb.top.m_axis.tdata)
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [run_test_tuser_assert]:
|
||||
factory = TestFactory(test)
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("reg_type", [0, 1, 2])
|
||||
@pytest.mark.parametrize("data_w", [8, 16, 32])
|
||||
def test_taxi_axis_register(request, data_w, reg_type):
|
||||
dut = "taxi_axis_register"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(rtl_dir, "taxi_axis_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['KEEP_EN'] = int(parameters['DATA_W'] > 8)
|
||||
parameters['KEEP_W'] = (parameters['DATA_W'] + 7) // 8
|
||||
parameters['STRB_EN'] = 0
|
||||
parameters['LAST_EN'] = 1
|
||||
parameters['ID_EN'] = 1
|
||||
parameters['ID_W'] = 8
|
||||
parameters['DEST_EN'] = 1
|
||||
parameters['DEST_W'] = 8
|
||||
parameters['USER_EN'] = 1
|
||||
parameters['USER_W'] = 1
|
||||
parameters['REG_TYPE'] = reg_type
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
74
src/axis/tb/taxi_axis_register/test_taxi_axis_register.sv
Normal file
74
src/axis/tb/taxi_axis_register/test_taxi_axis_register.sv
Normal file
@@ -0,0 +1,74 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4-Stream register testbench
|
||||
*/
|
||||
module test_taxi_axis_register #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DATA_W = 8,
|
||||
parameter logic KEEP_EN = (DATA_W>8),
|
||||
parameter KEEP_W = ((DATA_W+7)/8),
|
||||
parameter logic STRB_EN = 1'b0,
|
||||
parameter logic LAST_EN = 1'b1,
|
||||
parameter logic ID_EN = 1'b0,
|
||||
parameter ID_W = 8,
|
||||
parameter logic DEST_EN = 1'b0,
|
||||
parameter DEST_W = 8,
|
||||
parameter logic USER_EN = 1'b1,
|
||||
parameter USER_W = 1,
|
||||
parameter REG_TYPE = 2
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.KEEP_EN(KEEP_EN),
|
||||
.KEEP_W(KEEP_W),
|
||||
.STRB_EN(STRB_EN),
|
||||
.LAST_EN(LAST_EN),
|
||||
.ID_EN(ID_EN),
|
||||
.ID_W(ID_W),
|
||||
.DEST_EN(DEST_EN),
|
||||
.DEST_W(DEST_W),
|
||||
.USER_EN(USER_EN),
|
||||
.USER_W(USER_W)
|
||||
) s_axis(), m_axis();
|
||||
|
||||
taxi_axis_register #(
|
||||
.REG_TYPE(REG_TYPE)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Stream input (sink)
|
||||
*/
|
||||
.s_axis(s_axis),
|
||||
|
||||
/*
|
||||
* AXI4-Stream output (source)
|
||||
*/
|
||||
.m_axis(m_axis)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user