Reorganize repository
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
561
src/eth/rtl/taxi_axis_gmii_rx.sv
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561
src/eth/rtl/taxi_axis_gmii_rx.sv
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@@ -0,0 +1,561 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2015-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4-Stream GMII frame receiver (GMII in, AXI out)
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*/
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module taxi_axis_gmii_rx #
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(
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parameter DATA_W = 8,
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parameter logic PTP_TS_EN = 1'b0,
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parameter PTP_TS_W = 96
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* GMII input
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*/
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input wire logic [DATA_W-1:0] gmii_rxd,
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input wire logic gmii_rx_dv,
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input wire logic gmii_rx_er,
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/*
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* Receive interface (AXI stream)
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*/
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taxi_axis_if.src m_axis_rx,
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/*
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* PTP
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*/
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input wire logic [PTP_TS_W-1:0] ptp_ts,
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/*
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* Control
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*/
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input wire logic clk_enable,
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input wire logic mii_select,
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/*
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* Configuration
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*/
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input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518,
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input wire logic cfg_rx_enable,
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/*
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* Status
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*/
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output wire logic rx_start_packet,
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output wire logic stat_rx_byte,
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output wire logic [15:0] stat_rx_pkt_len,
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output wire logic stat_rx_pkt_fragment,
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output wire logic stat_rx_pkt_jabber,
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output wire logic stat_rx_pkt_ucast,
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output wire logic stat_rx_pkt_mcast,
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output wire logic stat_rx_pkt_bcast,
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output wire logic stat_rx_pkt_vlan,
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output wire logic stat_rx_pkt_good,
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output wire logic stat_rx_pkt_bad,
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output wire logic stat_rx_err_oversize,
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output wire logic stat_rx_err_bad_fcs,
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output wire logic stat_rx_err_bad_block,
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output wire logic stat_rx_err_framing,
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output wire logic stat_rx_err_preamble
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);
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localparam USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
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// check configuration
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if (DATA_W != 8)
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$fatal(0, "Error: Interface width must be 8 (instance %m)");
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if (m_axis_rx.DATA_W != DATA_W)
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$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
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if (m_axis_rx.USER_W != USER_W)
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$fatal(0, "Error: Interface USER_W parameter mismatch (instance %m)");
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localparam [7:0]
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ETH_PRE = 8'h55,
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ETH_SFD = 8'hD5;
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localparam [1:0]
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STATE_IDLE = 2'd0,
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STATE_PIPE = 2'd1,
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STATE_PAYLOAD = 2'd2;
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logic [1:0] state_reg = STATE_IDLE, state_next;
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// datapath control signals
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logic reset_crc;
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logic update_crc;
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logic mii_odd = 1'b0;
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logic in_frame = 1'b0;
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logic [DATA_W-1:0] gmii_rxd_d0 = '0;
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logic [DATA_W-1:0] gmii_rxd_d1 = '0;
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logic [DATA_W-1:0] gmii_rxd_d2 = '0;
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logic [DATA_W-1:0] gmii_rxd_d3 = '0;
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logic [DATA_W-1:0] gmii_rxd_d4 = '0;
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logic gmii_rx_dv_d0 = 1'b0;
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logic gmii_rx_dv_d1 = 1'b0;
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logic gmii_rx_dv_d2 = 1'b0;
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logic gmii_rx_dv_d3 = 1'b0;
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logic gmii_rx_dv_d4 = 1'b0;
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logic gmii_rx_er_d0 = 1'b0;
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logic gmii_rx_er_d1 = 1'b0;
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logic gmii_rx_er_d2 = 1'b0;
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logic gmii_rx_er_d3 = 1'b0;
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logic gmii_rx_er_d4 = 1'b0;
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logic frame_error_reg = 1'b0, frame_error_next;
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logic in_pre_reg = 1'b0, in_pre_next;
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logic pre_ok_reg = 1'b0, pre_ok_next;
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logic [3:0] hdr_ptr_reg = '0, hdr_ptr_next;
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logic is_mcast_reg = 1'b0, is_mcast_next;
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logic is_bcast_reg = 1'b0, is_bcast_next;
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logic is_8021q_reg = 1'b0, is_8021q_next;
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logic [15:0] frame_len_reg = '0, frame_len_next;
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logic [15:0] frame_len_lim_reg = '0, frame_len_lim_next;
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logic [DATA_W-1:0] m_axis_rx_tdata_reg = '0, m_axis_rx_tdata_next;
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logic m_axis_rx_tvalid_reg = 1'b0, m_axis_rx_tvalid_next;
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logic m_axis_rx_tlast_reg = 1'b0, m_axis_rx_tlast_next;
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logic m_axis_rx_tuser_reg = 1'b0, m_axis_rx_tuser_next;
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logic start_packet_int_reg = 1'b0;
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logic start_packet_reg = 1'b0;
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logic stat_rx_byte_reg = 1'b0, stat_rx_byte_next;
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logic [15:0] stat_rx_pkt_len_reg = '0, stat_rx_pkt_len_next;
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logic stat_rx_pkt_fragment_reg = 1'b0, stat_rx_pkt_fragment_next;
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logic stat_rx_pkt_jabber_reg = 1'b0, stat_rx_pkt_jabber_next;
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logic stat_rx_pkt_ucast_reg = 1'b0, stat_rx_pkt_ucast_next;
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logic stat_rx_pkt_mcast_reg = 1'b0, stat_rx_pkt_mcast_next;
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logic stat_rx_pkt_bcast_reg = 1'b0, stat_rx_pkt_bcast_next;
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logic stat_rx_pkt_vlan_reg = 1'b0, stat_rx_pkt_vlan_next;
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logic stat_rx_pkt_good_reg = 1'b0, stat_rx_pkt_good_next;
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logic stat_rx_pkt_bad_reg = 1'b0, stat_rx_pkt_bad_next;
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logic stat_rx_err_oversize_reg = 1'b0, stat_rx_err_oversize_next;
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logic stat_rx_err_bad_fcs_reg = 1'b0, stat_rx_err_bad_fcs_next;
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logic stat_rx_err_bad_block_reg = 1'b0, stat_rx_err_bad_block_next;
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logic stat_rx_err_framing_reg = 1'b0, stat_rx_err_framing_next;
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logic stat_rx_err_preamble_reg = 1'b0, stat_rx_err_preamble_next;
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logic [PTP_TS_W-1:0] ptp_ts_out_reg = '0;
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logic [31:0] crc_state = '1;
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wire [31:0] crc_next;
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assign m_axis_rx.tdata = m_axis_rx_tdata_reg;
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assign m_axis_rx.tkeep = 1'b1;
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assign m_axis_rx.tstrb = m_axis_rx.tkeep;
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assign m_axis_rx.tvalid = m_axis_rx_tvalid_reg;
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assign m_axis_rx.tlast = m_axis_rx_tlast_reg;
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assign m_axis_rx.tid = '0;
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assign m_axis_rx.tdest = '0;
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assign m_axis_rx.tuser[0] = m_axis_rx_tuser_reg;
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if (PTP_TS_EN) begin
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assign m_axis_rx.tuser[1 +: PTP_TS_W] = ptp_ts_out_reg;
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end
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assign rx_start_packet = start_packet_reg;
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assign stat_rx_byte = stat_rx_byte_reg;
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assign stat_rx_pkt_len = stat_rx_pkt_len_reg;
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assign stat_rx_pkt_fragment = stat_rx_pkt_fragment_reg;
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assign stat_rx_pkt_jabber = stat_rx_pkt_jabber_reg;
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assign stat_rx_pkt_ucast = stat_rx_pkt_ucast_reg;
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assign stat_rx_pkt_mcast = stat_rx_pkt_mcast_reg;
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assign stat_rx_pkt_bcast = stat_rx_pkt_bcast_reg;
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assign stat_rx_pkt_vlan = stat_rx_pkt_vlan_reg;
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assign stat_rx_pkt_good = stat_rx_pkt_good_reg;
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assign stat_rx_pkt_bad = stat_rx_pkt_bad_reg;
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assign stat_rx_err_oversize = stat_rx_err_oversize_reg;
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assign stat_rx_err_bad_fcs = stat_rx_err_bad_fcs_reg;
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assign stat_rx_err_bad_block = stat_rx_err_bad_block_reg;
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assign stat_rx_err_framing = stat_rx_err_framing_reg;
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assign stat_rx_err_preamble = stat_rx_err_preamble_reg;
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taxi_lfsr #(
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.LFSR_W(32),
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.LFSR_POLY(32'h4c11db7),
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.LFSR_GALOIS(1),
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.LFSR_FEED_FORWARD(0),
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.REVERSE(1),
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.DATA_W(8)
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)
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eth_crc_8 (
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.data_in(gmii_rxd_d0),
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.state_in(crc_state),
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.data_out(),
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.state_out(crc_next)
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);
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wire crc_valid = crc_next == ~32'h2144df1c;
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always_comb begin
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state_next = STATE_IDLE;
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reset_crc = 1'b0;
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update_crc = 1'b0;
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frame_error_next = frame_error_reg;
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in_pre_next = in_pre_reg;
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pre_ok_next = pre_ok_reg;
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hdr_ptr_next = hdr_ptr_reg;
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is_mcast_next = is_mcast_reg;
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is_bcast_next = is_bcast_reg;
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is_8021q_next = is_8021q_reg;
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frame_len_next = frame_len_reg;
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frame_len_lim_next = frame_len_lim_reg;
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m_axis_rx_tdata_next = '0;
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m_axis_rx_tvalid_next = 1'b0;
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m_axis_rx_tlast_next = 1'b0;
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m_axis_rx_tuser_next = 1'b0;
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stat_rx_byte_next = 1'b0;
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stat_rx_pkt_len_next = '0;
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stat_rx_pkt_fragment_next = 1'b0;
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stat_rx_pkt_jabber_next = 1'b0;
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stat_rx_pkt_ucast_next = 1'b0;
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stat_rx_pkt_mcast_next = 1'b0;
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stat_rx_pkt_bcast_next = 1'b0;
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stat_rx_pkt_vlan_next = 1'b0;
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stat_rx_pkt_good_next = 1'b0;
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stat_rx_pkt_bad_next = 1'b0;
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stat_rx_err_oversize_next = 1'b0;
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stat_rx_err_bad_fcs_next = 1'b0;
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stat_rx_err_bad_block_next = 1'b0;
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stat_rx_err_framing_next = 1'b0;
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stat_rx_err_preamble_next = 1'b0;
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if (!clk_enable) begin
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// clock disabled - hold state
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state_next = state_reg;
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end else if (mii_select && !mii_odd) begin
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// MII even cycle - hold state
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state_next = state_reg;
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end else begin
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// counter to measure frame length
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if (&frame_len_reg == 0) begin
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frame_len_next = frame_len_reg + 1;
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end
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// counter for max frame length enforcement
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if (frame_len_lim_reg != 0) begin
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frame_len_lim_next = frame_len_lim_reg - 1;
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end
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// address and ethertype checks
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if (&hdr_ptr_reg == 0) begin
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hdr_ptr_next = hdr_ptr_reg + 1;
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end
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case (hdr_ptr_reg)
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4'd0: begin
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is_mcast_next = gmii_rxd_d4[0];
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is_bcast_next = gmii_rxd_d4 == 8'hff;
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end
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4'd1: is_bcast_next = is_bcast_reg && gmii_rxd_d4 == 8'hff;
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4'd2: is_bcast_next = is_bcast_reg && gmii_rxd_d4 == 8'hff;
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4'd3: is_bcast_next = is_bcast_reg && gmii_rxd_d4 == 8'hff;
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4'd4: is_bcast_next = is_bcast_reg && gmii_rxd_d4 == 8'hff;
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4'd5: is_bcast_next = is_bcast_reg && gmii_rxd_d4 == 8'hff;
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4'd12: is_8021q_next = gmii_rxd_d4 == 8'h81;
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4'd13: is_8021q_next = is_8021q_reg && gmii_rxd_d4 == 8'h00;
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default: begin
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// do nothing
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end
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endcase
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case (state_reg)
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STATE_IDLE: begin
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// idle state - wait for packet
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reset_crc = 1'b1;
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frame_error_next = 1'b0;
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frame_len_next = 1;
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frame_len_lim_next = cfg_rx_max_pkt_len;
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hdr_ptr_next = 0;
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is_mcast_next = 1'b0;
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is_bcast_next = 1'b0;
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is_8021q_next = 1'b0;
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state_next = STATE_IDLE;
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if (gmii_rx_dv_d0) begin
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if (gmii_rx_er_d0) begin
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// error in preamble
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in_pre_next = 1'b0;
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pre_ok_next = 1'b0;
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stat_rx_err_framing_next = 1'b1;
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end else if (gmii_rxd_d0 == ETH_PRE) begin
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// normal preamble
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end else if (gmii_rxd_d0 == ETH_SFD) begin
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// start
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in_pre_next = 1'b0;
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if (in_pre_reg && cfg_rx_enable) begin
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stat_rx_byte_next = 1'b1;
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state_next = STATE_PIPE;
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end
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end else begin
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// abnormal preamble
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pre_ok_next = 1'b0;
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end
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end else begin
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// reset and wait for data
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in_pre_next = 1'b1;
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pre_ok_next = 1'b1;
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end
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end
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STATE_PIPE: begin
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// wait for FCS pipeline to fill
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update_crc = 1'b1;
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hdr_ptr_next = 0;
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is_mcast_next = 1'b0;
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is_bcast_next = 1'b0;
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is_8021q_next = 1'b0;
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stat_rx_byte_next = gmii_rx_dv;
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if (gmii_rx_dv && gmii_rx_er) begin
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frame_error_next = 1'b1;
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stat_rx_err_framing_next = 1'b1;
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end
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if (gmii_rx_dv_d4 && !gmii_rx_er_d4 && gmii_rxd_d4 == ETH_SFD) begin
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state_next = STATE_PAYLOAD;
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end else begin
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state_next = STATE_PIPE;
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end
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end
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STATE_PAYLOAD: begin
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// read payload
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update_crc = 1'b1;
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m_axis_rx_tdata_next = gmii_rxd_d4;
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m_axis_rx_tvalid_next = 1'b1;
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stat_rx_byte_next = gmii_rx_dv;
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if (gmii_rx_dv && gmii_rx_er) begin
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frame_error_next = 1'b1;
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stat_rx_err_framing_next = 1'b1;
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end
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if (!gmii_rx_dv) begin
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// end of packet
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m_axis_rx_tlast_next = 1'b1;
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stat_rx_pkt_len_next = frame_len_reg;
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stat_rx_pkt_ucast_next = !is_mcast_reg;
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stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
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stat_rx_pkt_bcast_next = is_bcast_reg;
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stat_rx_pkt_vlan_next = is_8021q_reg;
|
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stat_rx_err_oversize_next = frame_len_lim_reg == 0;
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stat_rx_err_framing_next = !gmii_rx_dv_d0;
|
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stat_rx_err_preamble_next = !pre_ok_reg;
|
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if (frame_error_next) begin
|
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// error
|
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m_axis_rx_tuser_next = 1'b1;
|
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stat_rx_pkt_fragment_next = frame_len_reg[15:6] == 0;
|
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stat_rx_pkt_jabber_next = frame_len_lim_reg == 0;
|
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stat_rx_pkt_bad_next = 1'b1;
|
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end else if (crc_valid) begin
|
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// FCS good
|
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if (frame_len_lim_reg == 0) begin
|
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// too long
|
||||
m_axis_rx_tuser_next = 1'b1;
|
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stat_rx_pkt_bad_next = 1'b1;
|
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end else begin
|
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// length OK
|
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m_axis_rx_tuser_next = 1'b0;
|
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stat_rx_pkt_good_next = 1'b1;
|
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end
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end else begin
|
||||
// FCS bad
|
||||
m_axis_rx_tuser_next = 1'b1;
|
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stat_rx_pkt_fragment_next = frame_len_reg[15:6] == 0;
|
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stat_rx_pkt_jabber_next = frame_len_lim_reg == 0;
|
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stat_rx_pkt_bad_next = 1'b1;
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stat_rx_err_bad_fcs_next = 1'b1;
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end
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reset_crc = 1'b1;
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state_next = STATE_IDLE;
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end else begin
|
||||
state_next = STATE_PAYLOAD;
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
// invalid state, return to idle
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
state_reg <= state_next;
|
||||
|
||||
frame_error_reg <= frame_error_next;
|
||||
in_pre_reg <= in_pre_next;
|
||||
pre_ok_reg <= pre_ok_next;
|
||||
hdr_ptr_reg <= hdr_ptr_next;
|
||||
is_mcast_reg <= is_mcast_next;
|
||||
is_bcast_reg <= is_bcast_next;
|
||||
is_8021q_reg <= is_8021q_next;
|
||||
frame_len_reg <= frame_len_next;
|
||||
frame_len_lim_reg <= frame_len_lim_next;
|
||||
|
||||
m_axis_rx_tdata_reg <= m_axis_rx_tdata_next;
|
||||
m_axis_rx_tvalid_reg <= m_axis_rx_tvalid_next;
|
||||
m_axis_rx_tlast_reg <= m_axis_rx_tlast_next;
|
||||
m_axis_rx_tuser_reg <= m_axis_rx_tuser_next;
|
||||
|
||||
start_packet_int_reg <= 1'b0;
|
||||
start_packet_reg <= 1'b0;
|
||||
|
||||
if (start_packet_int_reg) begin
|
||||
ptp_ts_out_reg <= ptp_ts;
|
||||
start_packet_reg <= 1'b1;
|
||||
end
|
||||
|
||||
if (clk_enable) begin
|
||||
if (mii_select) begin
|
||||
mii_odd <= !mii_odd || !gmii_rx_dv;
|
||||
|
||||
if (in_frame) begin
|
||||
in_frame <= gmii_rx_dv;
|
||||
end else if (gmii_rx_dv && {gmii_rxd[3:0], gmii_rxd_d0[7:4]} == ETH_SFD) begin
|
||||
in_frame <= 1'b1;
|
||||
start_packet_int_reg <= 1'b1;
|
||||
mii_odd <= 1'b1;
|
||||
end
|
||||
|
||||
gmii_rxd_d0 <= {gmii_rxd[3:0], gmii_rxd_d0[7:4]};
|
||||
|
||||
if (mii_odd) begin
|
||||
gmii_rxd_d1 <= gmii_rxd_d0;
|
||||
gmii_rxd_d2 <= gmii_rxd_d1;
|
||||
gmii_rxd_d3 <= gmii_rxd_d2;
|
||||
gmii_rxd_d4 <= gmii_rxd_d3;
|
||||
|
||||
gmii_rx_dv_d0 <= gmii_rx_dv;
|
||||
gmii_rx_dv_d1 <= gmii_rx_dv_d0;
|
||||
gmii_rx_dv_d2 <= gmii_rx_dv_d1;
|
||||
gmii_rx_dv_d3 <= gmii_rx_dv_d2;
|
||||
gmii_rx_dv_d4 <= gmii_rx_dv_d3;
|
||||
|
||||
gmii_rx_er_d0 <= gmii_rx_er;
|
||||
gmii_rx_er_d1 <= gmii_rx_er_d0;
|
||||
gmii_rx_er_d2 <= gmii_rx_er_d1;
|
||||
gmii_rx_er_d3 <= gmii_rx_er_d2;
|
||||
gmii_rx_er_d4 <= gmii_rx_er_d3;
|
||||
end else begin
|
||||
gmii_rx_dv_d0 <= gmii_rx_dv & gmii_rx_dv_d0;
|
||||
gmii_rx_er_d0 <= gmii_rx_er | gmii_rx_er_d0;
|
||||
end
|
||||
end else begin
|
||||
if (in_frame) begin
|
||||
in_frame <= gmii_rx_dv;
|
||||
end else if (gmii_rx_dv && gmii_rxd == ETH_SFD) begin
|
||||
in_frame <= 1'b1;
|
||||
start_packet_int_reg <= 1'b1;
|
||||
end
|
||||
|
||||
gmii_rxd_d0 <= gmii_rxd;
|
||||
gmii_rxd_d1 <= gmii_rxd_d0;
|
||||
gmii_rxd_d2 <= gmii_rxd_d1;
|
||||
gmii_rxd_d3 <= gmii_rxd_d2;
|
||||
gmii_rxd_d4 <= gmii_rxd_d3;
|
||||
|
||||
gmii_rx_dv_d0 <= gmii_rx_dv;
|
||||
gmii_rx_dv_d1 <= gmii_rx_dv_d0;
|
||||
gmii_rx_dv_d2 <= gmii_rx_dv_d1;
|
||||
gmii_rx_dv_d3 <= gmii_rx_dv_d2;
|
||||
gmii_rx_dv_d4 <= gmii_rx_dv_d3;
|
||||
|
||||
gmii_rx_er_d0 <= gmii_rx_er;
|
||||
gmii_rx_er_d1 <= gmii_rx_er_d0;
|
||||
gmii_rx_er_d2 <= gmii_rx_er_d1;
|
||||
gmii_rx_er_d3 <= gmii_rx_er_d2;
|
||||
gmii_rx_er_d4 <= gmii_rx_er_d3;
|
||||
end
|
||||
end
|
||||
|
||||
if (reset_crc) begin
|
||||
crc_state <= '1;
|
||||
end else if (update_crc) begin
|
||||
crc_state <= crc_next;
|
||||
end
|
||||
|
||||
stat_rx_byte_reg <= stat_rx_byte_next;
|
||||
stat_rx_pkt_len_reg <= stat_rx_pkt_len_next;
|
||||
stat_rx_pkt_fragment_reg <= stat_rx_pkt_fragment_next;
|
||||
stat_rx_pkt_jabber_reg <= stat_rx_pkt_jabber_next;
|
||||
stat_rx_pkt_ucast_reg <= stat_rx_pkt_ucast_next;
|
||||
stat_rx_pkt_mcast_reg <= stat_rx_pkt_mcast_next;
|
||||
stat_rx_pkt_bcast_reg <= stat_rx_pkt_bcast_next;
|
||||
stat_rx_pkt_vlan_reg <= stat_rx_pkt_vlan_next;
|
||||
stat_rx_pkt_good_reg <= stat_rx_pkt_good_next;
|
||||
stat_rx_pkt_bad_reg <= stat_rx_pkt_bad_next;
|
||||
stat_rx_err_oversize_reg <= stat_rx_err_oversize_next;
|
||||
stat_rx_err_bad_fcs_reg <= stat_rx_err_bad_fcs_next;
|
||||
stat_rx_err_bad_block_reg <= stat_rx_err_bad_block_next;
|
||||
stat_rx_err_framing_reg <= stat_rx_err_framing_next;
|
||||
stat_rx_err_preamble_reg <= stat_rx_err_preamble_next;
|
||||
|
||||
if (rst) begin
|
||||
state_reg <= STATE_IDLE;
|
||||
|
||||
m_axis_rx_tvalid_reg <= 1'b0;
|
||||
|
||||
start_packet_int_reg <= 1'b0;
|
||||
start_packet_reg <= 1'b0;
|
||||
|
||||
stat_rx_byte_reg <= 1'b0;
|
||||
stat_rx_pkt_len_reg <= '0;
|
||||
stat_rx_pkt_fragment_reg <= 1'b0;
|
||||
stat_rx_pkt_jabber_reg <= 1'b0;
|
||||
stat_rx_pkt_ucast_reg <= 1'b0;
|
||||
stat_rx_pkt_mcast_reg <= 1'b0;
|
||||
stat_rx_pkt_bcast_reg <= 1'b0;
|
||||
stat_rx_pkt_vlan_reg <= 1'b0;
|
||||
stat_rx_pkt_good_reg <= 1'b0;
|
||||
stat_rx_pkt_bad_reg <= 1'b0;
|
||||
stat_rx_err_oversize_reg <= 1'b0;
|
||||
stat_rx_err_bad_fcs_reg <= 1'b0;
|
||||
stat_rx_err_bad_block_reg <= 1'b0;
|
||||
stat_rx_err_framing_reg <= 1'b0;
|
||||
stat_rx_err_preamble_reg <= 1'b0;
|
||||
|
||||
in_frame <= 1'b0;
|
||||
mii_odd <= 1'b0;
|
||||
|
||||
gmii_rx_dv_d0 <= 1'b0;
|
||||
gmii_rx_dv_d1 <= 1'b0;
|
||||
gmii_rx_dv_d2 <= 1'b0;
|
||||
gmii_rx_dv_d3 <= 1'b0;
|
||||
gmii_rx_dv_d4 <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user