axis: Add AXI stream concatenator module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
407
src/axis/rtl/taxi_axis_concat.sv
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407
src/axis/rtl/taxi_axis_concat.sv
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@@ -0,0 +1,407 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4-Stream frame concatenator
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*/
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module taxi_axis_concat #
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(
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// Number of AXI stream inputs
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parameter S_COUNT = 4
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI4-Stream inputs (sinks)
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*/
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taxi_axis_if.snk s_axis[S_COUNT],
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/*
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* AXI4-Stream output (source)
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*/
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taxi_axis_if.src m_axis
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);
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// extract parameters
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localparam DATA_W = s_axis[0].DATA_W;
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localparam logic KEEP_EN = s_axis[0].KEEP_EN && m_axis.KEEP_EN;
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localparam KEEP_W = s_axis[0].KEEP_W;
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localparam logic STRB_EN = s_axis[0].STRB_EN && m_axis.STRB_EN;
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localparam logic LAST_EN = s_axis[0].LAST_EN && m_axis.LAST_EN;
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localparam logic ID_EN = s_axis[0].ID_EN && m_axis.ID_EN;
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localparam ID_W = s_axis[0].ID_W;
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localparam logic DEST_EN = s_axis[0].DEST_EN && m_axis.DEST_EN;
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localparam DEST_W = s_axis[0].DEST_W;
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localparam logic USER_EN = s_axis[0].USER_EN && m_axis.USER_EN;
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localparam USER_W = s_axis[0].USER_W;
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localparam BYTE_LANES = KEEP_EN ? KEEP_W : 1;
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localparam BYTE_SIZE = DATA_W / BYTE_LANES;
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localparam CL_S_COUNT = $clog2(S_COUNT);
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localparam CL_BYTE_LANES = $clog2(BYTE_LANES);
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// check configuration
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if (m_axis.DATA_W != DATA_W)
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$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
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if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
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$fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
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if (BYTE_SIZE * BYTE_LANES != DATA_W)
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$fatal(0, "Error: input data width not evenly divisible (instance %m)");
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// internal datapath
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logic [DATA_W-1:0] m_axis_tdata_int;
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logic [KEEP_W-1:0] m_axis_tkeep_int;
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logic [KEEP_W-1:0] m_axis_tstrb_int;
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logic m_axis_tvalid_int;
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logic m_axis_tready_int_reg = 1'b0;
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logic m_axis_tlast_int;
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logic [ID_W-1:0] m_axis_tid_int;
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logic [DEST_W-1:0] m_axis_tdest_int;
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logic [USER_W-1:0] m_axis_tuser_int;
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wire m_axis_tready_int_early;
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if (S_COUNT == 1) begin
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// degenerate case
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assign s_axis[0].tready = m_axis_tready_int_reg;
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always_comb begin
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// pass through selected packet data
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m_axis_tdata_int = s_axis[0].tdata;
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m_axis_tkeep_int = s_axis[0].tkeep;
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m_axis_tstrb_int = s_axis[0].tstrb;
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m_axis_tvalid_int = s_axis[0].tvalid && m_axis_tready_int_reg;
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m_axis_tlast_int = s_axis[0].tlast;
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m_axis_tid_int = s_axis[0].tid;
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m_axis_tdest_int = s_axis[0].tdest;
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m_axis_tuser_int = s_axis[0].tuser;
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end
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end else begin
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logic output_ready;
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// unpack interface array
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wire [DATA_W-1:0] s_axis_tdata[S_COUNT];
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wire [KEEP_W-1:0] s_axis_tkeep[S_COUNT];
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wire [KEEP_W-1:0] s_axis_tstrb[S_COUNT];
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wire [S_COUNT-1:0] s_axis_tvalid;
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wire [S_COUNT-1:0] s_axis_tready;
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wire [S_COUNT-1:0] s_axis_tlast;
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wire [ID_W-1:0] s_axis_tid[S_COUNT];
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wire [DEST_W-1:0] s_axis_tdest[S_COUNT];
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wire [USER_W-1:0] s_axis_tuser[S_COUNT];
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for (genvar n = 0; n < S_COUNT; n = n + 1) begin
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assign s_axis_tdata[n] = s_axis[n].tdata;
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assign s_axis_tkeep[n] = s_axis[n].tkeep;
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assign s_axis_tstrb[n] = s_axis[n].tstrb;
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assign s_axis_tvalid[n] = s_axis[n].tvalid;
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assign s_axis[n].tready = s_axis_tready[n];
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assign s_axis_tlast[n] = s_axis[n].tlast;
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assign s_axis_tid[n] = s_axis[n].tid;
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assign s_axis_tdest[n] = s_axis[n].tdest;
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assign s_axis_tuser[n] = s_axis[n].tuser;
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end
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// destripe
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logic [CL_S_COUNT-1:0] select_reg = '0, select_next;
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reg [S_COUNT-1:0] s_axis_tready_reg = 0, s_axis_tready_next;
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assign s_axis_tready = s_axis_tready_reg;
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// mux for incoming packet
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wire [DATA_W-1:0] current_s_tdata = s_axis_tdata[select_reg];
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wire [KEEP_W-1:0] current_s_tkeep = s_axis_tkeep[select_reg];
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wire [KEEP_W-1:0] current_s_tstrb = s_axis_tstrb[select_reg];
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wire current_s_tvalid = s_axis_tvalid[select_reg];
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wire current_s_tready = s_axis_tready != 0;
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wire current_s_tlast = s_axis_tlast[select_reg];
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wire [ID_W-1:0] current_s_tid = s_axis_tid[select_reg];
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wire [DEST_W-1:0] current_s_tdest = s_axis_tdest[select_reg];
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wire [USER_W-1:0] current_s_tuser = s_axis_tuser[select_reg];
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always_comb begin
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select_next = select_reg;
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s_axis_tready_next = '0;
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if (current_s_tvalid && current_s_tready) begin
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// move to next piece at end of frame
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if (current_s_tlast) begin
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if (select_reg < CL_S_COUNT'(S_COUNT-1)) begin
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select_next = select_reg + 1;
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end else begin
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select_next = '0;
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end
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end
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end
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// generate ready signal on selected port
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s_axis_tready_next[select_next] = m_axis_tready_int_early && output_ready;
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end
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always_ff @(posedge clk) begin
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select_reg <= select_next;
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s_axis_tready_reg <= s_axis_tready_next;
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if (rst) begin
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select_reg <= '0;
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s_axis_tready_reg <= '0;
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end
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end
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if (!KEEP_EN || BYTE_LANES == 1) begin
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// degenerate case
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assign output_ready = 1'b1;
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always_comb begin
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m_axis_tdata_int = current_s_tdata;
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m_axis_tkeep_int = current_s_tkeep;
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m_axis_tstrb_int = current_s_tstrb;
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m_axis_tvalid_int = current_s_tvalid && current_s_tready;
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m_axis_tlast_int = current_s_tlast && select_reg == CL_S_COUNT'(S_COUNT-1);
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m_axis_tid_int = current_s_tid;
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m_axis_tdest_int = current_s_tdest;
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m_axis_tuser_int = current_s_tuser;
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end
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end else begin
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// repack
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logic [2*DATA_W-1:0] tdata_reg = '0, tdata_next;
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logic [2*KEEP_W-1:0] tkeep_reg = '0, tkeep_next;
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logic [2*KEEP_W-1:0] tstrb_reg = '0, tstrb_next;
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logic [1:0] tvalid_reg = '0, tvalid_next;
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logic [1:0] tlast_reg = '0, tlast_next;
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logic [ID_W-1:0] tid_reg = '0, tid_next;
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logic [DEST_W-1:0] tdest_reg = '0, tdest_next;
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logic [USER_W-1:0] tuser_reg = '0, tuser_next;
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logic [CL_BYTE_LANES-1:0] offset_reg = '0, offset_next;
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logic [CL_BYTE_LANES+1-1:0] current_byte_count;
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always_comb begin
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current_byte_count = '0;
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for (integer k = 0; k < KEEP_W; k = k + 1) begin
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if (current_s_tkeep[k]) begin
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current_byte_count = (CL_BYTE_LANES+1)'(k+1);
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end
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end
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end
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always_comb begin
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tdata_next = tdata_reg;
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tkeep_next = tkeep_reg;
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tstrb_next = tstrb_reg;
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tvalid_next = tvalid_reg;
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tlast_next = tlast_reg;
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tid_next = tid_reg;
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tdest_next = tdest_reg;
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tuser_next = tuser_reg;
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offset_next = offset_reg;
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m_axis_tdata_int = tdata_reg[0 +: DATA_W];
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m_axis_tkeep_int = tkeep_reg[0 +: KEEP_W];
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m_axis_tstrb_int = tstrb_reg[0 +: KEEP_W];
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m_axis_tvalid_int = 1'b0;
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m_axis_tlast_int = tlast_reg[0];
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m_axis_tid_int = tid_reg;
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m_axis_tdest_int = tdest_reg;
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m_axis_tuser_int = tuser_reg;
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output_ready = !tlast_reg[1];
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if (m_axis_tready_int_reg && (tkeep_reg[KEEP_W-1] || tlast_reg[0])) begin
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// shift out full words
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tdata_next[0 +: DATA_W] = tdata_reg[DATA_W +: DATA_W];
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tkeep_next = {{KEEP_W{1'b0}}, tkeep_reg[KEEP_W +: KEEP_W]};
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tstrb_next = {{KEEP_W{1'b0}}, tstrb_reg[KEEP_W +: KEEP_W]};
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tvalid_next = {1'b0, tvalid_reg[1]};
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tlast_next = {1'b0, tlast_reg[1]};
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m_axis_tvalid_int = 1'b1;
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end
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if (current_s_tvalid && current_s_tready) begin
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// store data with offset
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tdata_next[offset_reg*BYTE_SIZE +: DATA_W] = current_s_tdata;
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tkeep_next[offset_reg*1 +: KEEP_W] = current_s_tkeep;
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tstrb_next[offset_reg*1 +: KEEP_W] = current_s_tstrb;
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tvalid_next[0] = 1'b1;
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tid_next = current_s_tid;
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tdest_next = current_s_tdest;
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tuser_next = current_s_tuser;
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// compute new offset (natural wrapping)
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offset_next = offset_reg + CL_BYTE_LANES'(current_byte_count);
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if (tkeep_next[KEEP_W +: KEEP_W] != 0) begin
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// wrapped to higher word
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tvalid_next[1] = 1'b1;
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end
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if (current_s_tlast && select_reg == CL_S_COUNT'(S_COUNT-1)) begin
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// end of frame
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offset_next = '0;
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if (tkeep_next[KEEP_W +: KEEP_W] != 0) begin
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tvalid_next[0] = 1'b1;
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tvalid_next[1] = 1'b1;
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tlast_next[1] = 1'b1;
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output_ready = 1'b0;
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end else begin
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tvalid_next[0] = 1'b1;
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tlast_next[0] = 1'b1;
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end
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end
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end
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end
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always_ff @(posedge clk) begin
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tdata_reg <= tdata_next;
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tkeep_reg <= tkeep_next;
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tstrb_reg <= tstrb_next;
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tvalid_reg <= tvalid_next;
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tlast_reg <= tlast_next;
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tid_reg <= tid_next;
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tdest_reg <= tdest_next;
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tuser_reg <= tuser_next;
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offset_reg <= offset_next;
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if (rst) begin
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tvalid_reg <= '0;
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offset_reg <= '0;
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end
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end
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end
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end
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// output datapath logic
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logic [DATA_W-1:0] m_axis_tdata_reg = '0;
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logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
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logic [KEEP_W-1:0] m_axis_tstrb_reg = '0;
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logic m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
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logic m_axis_tlast_reg = 1'b0;
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logic [ID_W-1:0] m_axis_tid_reg = '0;
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logic [DEST_W-1:0] m_axis_tdest_reg = '0;
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logic [USER_W-1:0] m_axis_tuser_reg = '0;
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logic [DATA_W-1:0] temp_m_axis_tdata_reg = '0;
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logic [KEEP_W-1:0] temp_m_axis_tkeep_reg = '0;
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logic [KEEP_W-1:0] temp_m_axis_tstrb_reg = '0;
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logic temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
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logic temp_m_axis_tlast_reg = 1'b0;
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logic [ID_W-1:0] temp_m_axis_tid_reg = '0;
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logic [DEST_W-1:0] temp_m_axis_tdest_reg = '0;
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logic [USER_W-1:0] temp_m_axis_tuser_reg = '0;
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// datapath control
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logic store_axis_int_to_output;
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logic store_axis_int_to_temp;
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logic store_axis_temp_to_output;
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assign m_axis.tdata = m_axis_tdata_reg;
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assign m_axis.tkeep = KEEP_EN ? m_axis_tkeep_reg : '1;
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assign m_axis.tstrb = STRB_EN ? m_axis_tstrb_reg : m_axis.tkeep;
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assign m_axis.tvalid = m_axis_tvalid_reg;
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assign m_axis.tlast = LAST_EN ? m_axis_tlast_reg : 1'b1;
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assign m_axis.tid = ID_EN ? m_axis_tid_reg : '0;
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assign m_axis.tdest = DEST_EN ? m_axis_tdest_reg : '0;
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assign m_axis.tuser = USER_EN ? m_axis_tuser_reg : '0;
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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assign m_axis_tready_int_early = m_axis.tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
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always_comb begin
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// transfer sink ready state to source
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m_axis_tvalid_next = m_axis_tvalid_reg;
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temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
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store_axis_int_to_output = 1'b0;
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store_axis_int_to_temp = 1'b0;
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store_axis_temp_to_output = 1'b0;
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if (m_axis_tready_int_reg) begin
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// input is ready
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if (m_axis.tready || !m_axis_tvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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m_axis_tvalid_next = m_axis_tvalid_int;
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store_axis_int_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_m_axis_tvalid_next = m_axis_tvalid_int;
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store_axis_int_to_temp = 1'b1;
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end
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end else if (m_axis.tready) begin
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// input is not ready, but output is ready
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m_axis_tvalid_next = temp_m_axis_tvalid_reg;
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temp_m_axis_tvalid_next = 1'b0;
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store_axis_temp_to_output = 1'b1;
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end
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end
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always_ff @(posedge clk) begin
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m_axis_tvalid_reg <= m_axis_tvalid_next;
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m_axis_tready_int_reg <= m_axis_tready_int_early;
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temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
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// datapath
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if (store_axis_int_to_output) begin
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m_axis_tdata_reg <= m_axis_tdata_int;
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m_axis_tkeep_reg <= m_axis_tkeep_int;
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m_axis_tstrb_reg <= m_axis_tstrb_int;
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m_axis_tlast_reg <= m_axis_tlast_int;
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m_axis_tid_reg <= m_axis_tid_int;
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m_axis_tdest_reg <= m_axis_tdest_int;
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m_axis_tuser_reg <= m_axis_tuser_int;
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end else if (store_axis_temp_to_output) begin
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m_axis_tdata_reg <= temp_m_axis_tdata_reg;
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m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
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m_axis_tstrb_reg <= temp_m_axis_tstrb_reg;
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m_axis_tlast_reg <= temp_m_axis_tlast_reg;
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m_axis_tid_reg <= temp_m_axis_tid_reg;
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m_axis_tdest_reg <= temp_m_axis_tdest_reg;
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m_axis_tuser_reg <= temp_m_axis_tuser_reg;
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end
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if (store_axis_int_to_temp) begin
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temp_m_axis_tdata_reg <= m_axis_tdata_int;
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temp_m_axis_tkeep_reg <= m_axis_tkeep_int;
|
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temp_m_axis_tstrb_reg <= m_axis_tstrb_int;
|
||||
temp_m_axis_tlast_reg <= m_axis_tlast_int;
|
||||
temp_m_axis_tid_reg <= m_axis_tid_int;
|
||||
temp_m_axis_tdest_reg <= m_axis_tdest_int;
|
||||
temp_m_axis_tuser_reg <= m_axis_tuser_int;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
m_axis_tvalid_reg <= 1'b0;
|
||||
m_axis_tready_int_reg <= 1'b0;
|
||||
temp_m_axis_tvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user