bslathi19/taxi-bsl
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

example/Arty: Add XFCP to Arty example design for monitoring and control

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-04-09 12:17:46 -07:00
parent abadd72b1d
commit ddf1b37f4e
5 changed files with 80 additions and 53 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
example/Arty/fpga/README.md
View File

@@ -4,10 +4,10 @@
This example design targets the Digilent Arty A7 FPGA board.
The design places a looped-back MAC on the BASE-T port, as well as a looped-back UART on the USB UART.
The design places a looped-back MAC on the BASE-T port, as well as XFCP on the USB UART for monitoring and control.
* USB UART
* Looped-back UART
* XFCP
* RJ-45 Ethernet port with TI DP83848J PHY
* Looped-back MAC via MII