bslathi19/taxi-bsl
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

eth: Add support for synchronous gearbox to PHY, MAC+PHY, and GT wrappers

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-05-30 21:14:54 -07:00
parent f31ba113d2
commit e4762b7a8c
76 changed files with 3853 additions and 1090 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/eth/rtl/us/taxi_eth_mac_25g_us.f
View File

@@ -1,4 +1,5 @@
taxi_eth_mac_25g_us.sv
taxi_eth_mac_25g_us_ch.sv
taxi_eth_phy_25g_us_gt.f
taxi_eth_phy_25g_us_gt_ll.f
../taxi_eth_mac_phy_10g.f

6
src/eth/rtl/us/taxi_eth_mac_25g_us.sv
View File

@@ -23,6 +23,9 @@ module taxi_eth_mac_25g_us #
parameter CNT = 4,
// GT config
parameter logic CFG_LOW_LATENCY = 0,
// GT type
parameter string GT_TYPE = "GTY",
@@ -333,6 +336,9 @@ for (genvar n = 0; n < CNT; n = n + 1) begin : ch
.HAS_COMMON(HAS_COMMON),
// GT config
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
// GT type
.GT_TYPE(GT_TYPE),

334
src/eth/rtl/us/taxi_eth_mac_25g_us_ch.sv
View File

@@ -23,6 +23,9 @@ module taxi_eth_mac_25g_us_ch #
parameter logic HAS_COMMON = 1'b1,
// GT config
parameter logic CFG_LOW_LATENCY = 0,
// GT type
parameter string GT_TYPE = "GTY",
@@ -278,130 +281,244 @@ localparam HDR_W = 2;
wire rx_reset_req;
wire [5:0] gt_txheader;
wire [63:0] gt_txdata;
wire gt_rxgearboxslip;
wire [5:0] gt_rxheader;
wire [1:0] gt_rxheadervalid;
wire [63:0] gt_rxdata;
wire [1:0] gt_rxdatavalid;
wire [DATA_W-1:0] serdes_tx_data;
wire serdes_tx_data_valid;
wire [HDR_W-1:0] serdes_tx_hdr;
wire serdes_tx_hdr_valid;
wire serdes_tx_gbx_req_start;
wire serdes_tx_gbx_req_stall;
wire serdes_tx_gbx_start;
wire [DATA_W-1:0] serdes_rx_data;
wire serdes_rx_data_valid;
wire [HDR_W-1:0] serdes_rx_hdr;
wire serdes_rx_hdr_valid;
wire serdes_rx_bitslip;
taxi_eth_phy_25g_us_gt #(
.SIM(SIM),
.VENDOR(VENDOR),
.FAMILY(FAMILY),
if (CFG_LOW_LATENCY) begin : gt
.HAS_COMMON(HAS_COMMON),
taxi_eth_phy_25g_us_gt_ll #(
.SIM(SIM),
.VENDOR(VENDOR),
.FAMILY(FAMILY),
// GT type
.GT_TYPE(GT_TYPE),
.HAS_COMMON(HAS_COMMON),
// PLL parameters
.QPLL0_PD(QPLL0_PD),
.QPLL1_PD(QPLL1_PD),
.QPLL0_EXT_CTRL(QPLL0_EXT_CTRL),
.QPLL1_EXT_CTRL(QPLL1_EXT_CTRL),
// GT type
.GT_TYPE(GT_TYPE),
// GT parameters
.GT_TX_PD(GT_TX_PD),
.GT_TX_QPLL_SEL(GT_TX_QPLL_SEL),
.GT_TX_POLARITY(GT_TX_POLARITY),
.GT_TX_ELECIDLE(GT_TX_ELECIDLE),
.GT_TX_INHIBIT(GT_TX_INHIBIT),
.GT_TX_DIFFCTRL(GT_TX_DIFFCTRL),
.GT_TX_MAINCURSOR(GT_TX_MAINCURSOR),
.GT_TX_POSTCURSOR(GT_TX_POSTCURSOR),
.GT_TX_PRECURSOR(GT_TX_PRECURSOR),
.GT_RX_PD(GT_RX_PD),
.GT_RX_QPLL_SEL(GT_RX_QPLL_SEL),
.GT_RX_LPM_EN(GT_RX_LPM_EN),
.GT_RX_POLARITY(GT_RX_POLARITY)
)
gt_inst (
.xcvr_ctrl_clk(xcvr_ctrl_clk),
.xcvr_ctrl_rst(xcvr_ctrl_rst),
// PLL parameters
.QPLL0_PD(QPLL0_PD),
.QPLL1_PD(QPLL1_PD),
.QPLL0_EXT_CTRL(QPLL0_EXT_CTRL),
.QPLL1_EXT_CTRL(QPLL1_EXT_CTRL),
/*
* Common
*/
.xcvr_gtpowergood_out(xcvr_gtpowergood_out),
// GT parameters
.GT_TX_PD(GT_TX_PD),
.GT_TX_QPLL_SEL(GT_TX_QPLL_SEL),
.GT_TX_POLARITY(GT_TX_POLARITY),
.GT_TX_ELECIDLE(GT_TX_ELECIDLE),
.GT_TX_INHIBIT(GT_TX_INHIBIT),
.GT_TX_DIFFCTRL(GT_TX_DIFFCTRL),
.GT_TX_MAINCURSOR(GT_TX_MAINCURSOR),
.GT_TX_POSTCURSOR(GT_TX_POSTCURSOR),
.GT_TX_PRECURSOR(GT_TX_PRECURSOR),
.GT_RX_PD(GT_RX_PD),
.GT_RX_QPLL_SEL(GT_RX_QPLL_SEL),
.GT_RX_LPM_EN(GT_RX_LPM_EN),
.GT_RX_POLARITY(GT_RX_POLARITY),
/*
* PLL out
*/
.xcvr_gtrefclk00_in(xcvr_gtrefclk00_in),
.xcvr_qpll0pd_in(xcvr_qpll0pd_in),
.xcvr_qpll0reset_in(xcvr_qpll0reset_in),
.xcvr_qpll0pcierate_in(xcvr_qpll0pcierate_in),
.xcvr_qpll0lock_out(xcvr_qpll0lock_out),
.xcvr_qpll0clk_out(xcvr_qpll0clk_out),
.xcvr_qpll0refclk_out(xcvr_qpll0refclk_out),
.xcvr_gtrefclk01_in(xcvr_gtrefclk01_in),
.xcvr_qpll1pd_in(xcvr_qpll1pd_in),
.xcvr_qpll1reset_in(xcvr_qpll1reset_in),
.xcvr_qpll1pcierate_in(xcvr_qpll1pcierate_in),
.xcvr_qpll1lock_out(xcvr_qpll1lock_out),
.xcvr_qpll1clk_out(xcvr_qpll1clk_out),
.xcvr_qpll1refclk_out(xcvr_qpll1refclk_out),
// MAC/PHY parameters
.DATA_W(DATA_W),
.HDR_W(HDR_W)
)
gt_inst (
.xcvr_ctrl_clk(xcvr_ctrl_clk),
.xcvr_ctrl_rst(xcvr_ctrl_rst),
/*
* PLL in
*/
.xcvr_qpll0lock_in(xcvr_qpll0lock_in),
.xcvr_qpll0clk_in(xcvr_qpll0clk_in),
.xcvr_qpll0refclk_in(xcvr_qpll0refclk_in),
.xcvr_qpll1lock_in(xcvr_qpll1lock_in),
.xcvr_qpll1clk_in(xcvr_qpll1clk_in),
.xcvr_qpll1refclk_in(xcvr_qpll1refclk_in),
/*
* Common
*/
.xcvr_gtpowergood_out(xcvr_gtpowergood_out),
/*
* Serial data
*/
.xcvr_txp(xcvr_txp),
.xcvr_txn(xcvr_txn),
.xcvr_rxp(xcvr_rxp),
.xcvr_rxn(xcvr_rxn),
/*
* PLL out
*/
.xcvr_gtrefclk00_in(xcvr_gtrefclk00_in),
.xcvr_qpll0pd_in(xcvr_qpll0pd_in),
.xcvr_qpll0reset_in(xcvr_qpll0reset_in),
.xcvr_qpll0pcierate_in(xcvr_qpll0pcierate_in),
.xcvr_qpll0lock_out(xcvr_qpll0lock_out),
.xcvr_qpll0clk_out(xcvr_qpll0clk_out),
.xcvr_qpll0refclk_out(xcvr_qpll0refclk_out),
.xcvr_gtrefclk01_in(xcvr_gtrefclk01_in),
.xcvr_qpll1pd_in(xcvr_qpll1pd_in),
.xcvr_qpll1reset_in(xcvr_qpll1reset_in),
.xcvr_qpll1pcierate_in(xcvr_qpll1pcierate_in),
.xcvr_qpll1lock_out(xcvr_qpll1lock_out),
.xcvr_qpll1clk_out(xcvr_qpll1clk_out),
.xcvr_qpll1refclk_out(xcvr_qpll1refclk_out),
/*
* GT user clocks
*/
.rx_clk(rx_clk),
.rx_rst_in(rx_rst_in || rx_reset_req),
.rx_rst_out(rx_rst_out),
.tx_clk(tx_clk),
.tx_rst_in(tx_rst_in),
.tx_rst_out(tx_rst_out),
/*
* PLL in
*/
.xcvr_qpll0lock_in(xcvr_qpll0lock_in),
.xcvr_qpll0clk_in(xcvr_qpll0clk_in),
.xcvr_qpll0refclk_in(xcvr_qpll0refclk_in),
.xcvr_qpll1lock_in(xcvr_qpll1lock_in),
.xcvr_qpll1clk_in(xcvr_qpll1clk_in),
.xcvr_qpll1refclk_in(xcvr_qpll1refclk_in),
/*
* Serdes interface
*/
.gt_txheader(gt_txheader),
.gt_txdata(gt_txdata),
.gt_rxgearboxslip(gt_rxgearboxslip),
.gt_rxheader(gt_rxheader),
.gt_rxheadervalid(gt_rxheadervalid),
.gt_rxdata(gt_rxdata),
.gt_rxdatavalid(gt_rxdatavalid)
);
/*
* Serial data
*/
.xcvr_txp(xcvr_txp),
.xcvr_txn(xcvr_txn),
.xcvr_rxp(xcvr_rxp),
.xcvr_rxn(xcvr_rxn),
wire [DATA_W-1:0] serdes_tx_data;
wire [HDR_W-1:0] serdes_tx_hdr;
wire [DATA_W-1:0] serdes_rx_data;
wire [HDR_W-1:0] serdes_rx_hdr;
wire serdes_rx_bitslip;
/*
* GT user clocks
*/
.rx_clk(rx_clk),
.rx_rst_in(rx_rst_in || rx_reset_req),
.rx_rst_out(rx_rst_out),
.tx_clk(tx_clk),
.tx_rst_in(tx_rst_in),
.tx_rst_out(tx_rst_out),
assign gt_txdata = serdes_tx_data;
assign gt_txheader = {4'd0, serdes_tx_hdr};
assign gt_rxgearboxslip = serdes_rx_bitslip;
/*
* Serdes interface
*/
.serdes_tx_data(serdes_tx_data),
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_data_valid(serdes_rx_data_valid),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_hdr_valid(serdes_rx_hdr_valid),
.serdes_rx_bitslip(serdes_rx_bitslip)
);
end else begin : gt
taxi_eth_phy_25g_us_gt #(
.SIM(SIM),
.VENDOR(VENDOR),
.FAMILY(FAMILY),
.HAS_COMMON(HAS_COMMON),
// GT type
.GT_TYPE(GT_TYPE),
// PLL parameters
.QPLL0_PD(QPLL0_PD),
.QPLL1_PD(QPLL1_PD),
.QPLL0_EXT_CTRL(QPLL0_EXT_CTRL),
.QPLL1_EXT_CTRL(QPLL1_EXT_CTRL),
// GT parameters
.GT_TX_PD(GT_TX_PD),
.GT_TX_QPLL_SEL(GT_TX_QPLL_SEL),
.GT_TX_POLARITY(GT_TX_POLARITY),
.GT_TX_ELECIDLE(GT_TX_ELECIDLE),
.GT_TX_INHIBIT(GT_TX_INHIBIT),
.GT_TX_DIFFCTRL(GT_TX_DIFFCTRL),
.GT_TX_MAINCURSOR(GT_TX_MAINCURSOR),
.GT_TX_POSTCURSOR(GT_TX_POSTCURSOR),
.GT_TX_PRECURSOR(GT_TX_PRECURSOR),
.GT_RX_PD(GT_RX_PD),
.GT_RX_QPLL_SEL(GT_RX_QPLL_SEL),
.GT_RX_LPM_EN(GT_RX_LPM_EN),
.GT_RX_POLARITY(GT_RX_POLARITY),
// MAC/PHY parameters
.DATA_W(DATA_W),
.HDR_W(HDR_W)
)
gt_inst (
.xcvr_ctrl_clk(xcvr_ctrl_clk),
.xcvr_ctrl_rst(xcvr_ctrl_rst),
/*
* Common
*/
.xcvr_gtpowergood_out(xcvr_gtpowergood_out),
/*
* PLL out
*/
.xcvr_gtrefclk00_in(xcvr_gtrefclk00_in),
.xcvr_qpll0pd_in(xcvr_qpll0pd_in),
.xcvr_qpll0reset_in(xcvr_qpll0reset_in),
.xcvr_qpll0pcierate_in(xcvr_qpll0pcierate_in),
.xcvr_qpll0lock_out(xcvr_qpll0lock_out),
.xcvr_qpll0clk_out(xcvr_qpll0clk_out),
.xcvr_qpll0refclk_out(xcvr_qpll0refclk_out),
.xcvr_gtrefclk01_in(xcvr_gtrefclk01_in),
.xcvr_qpll1pd_in(xcvr_qpll1pd_in),
.xcvr_qpll1reset_in(xcvr_qpll1reset_in),
.xcvr_qpll1pcierate_in(xcvr_qpll1pcierate_in),
.xcvr_qpll1lock_out(xcvr_qpll1lock_out),
.xcvr_qpll1clk_out(xcvr_qpll1clk_out),
.xcvr_qpll1refclk_out(xcvr_qpll1refclk_out),
/*
* PLL in
*/
.xcvr_qpll0lock_in(xcvr_qpll0lock_in),
.xcvr_qpll0clk_in(xcvr_qpll0clk_in),
.xcvr_qpll0refclk_in(xcvr_qpll0refclk_in),
.xcvr_qpll1lock_in(xcvr_qpll1lock_in),
.xcvr_qpll1clk_in(xcvr_qpll1clk_in),
.xcvr_qpll1refclk_in(xcvr_qpll1refclk_in),
/*
* Serial data
*/
.xcvr_txp(xcvr_txp),
.xcvr_txn(xcvr_txn),
.xcvr_rxp(xcvr_rxp),
.xcvr_rxn(xcvr_rxn),
/*
* GT user clocks
*/
.rx_clk(rx_clk),
.rx_rst_in(rx_rst_in || rx_reset_req),
.rx_rst_out(rx_rst_out),
.tx_clk(tx_clk),
.tx_rst_in(tx_rst_in),
.tx_rst_out(tx_rst_out),
/*
* Serdes interface
*/
.serdes_tx_data(serdes_tx_data),
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_data_valid(serdes_rx_data_valid),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_hdr_valid(serdes_rx_hdr_valid),
.serdes_rx_bitslip(serdes_rx_bitslip)
);
if (!SIM) begin
assign serdes_rx_data = gt_rxdata;
assign serdes_rx_hdr = gt_rxheader[1:0];
end
taxi_eth_mac_phy_10g #(
.DATA_W(DATA_W),
.HDR_W(HDR_W),
.TX_GBX_IF_EN(CFG_LOW_LATENCY),
.RX_GBX_IF_EN(CFG_LOW_LATENCY),
.PADDING_EN(PADDING_EN),
.DIC_EN(DIC_EN),
.MIN_FRAME_LEN(MIN_FRAME_LEN),
@@ -445,9 +562,16 @@ eth_mac_phy_10g_inst (
* Serdes interface
*/
.serdes_tx_data(serdes_tx_data),
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_data_valid(serdes_rx_data_valid),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_hdr_valid(serdes_rx_hdr_valid),
.serdes_rx_bitslip(serdes_rx_bitslip),
.serdes_rx_reset_req(rx_reset_req),

57
src/eth/rtl/us/taxi_eth_phy_25g_us_gt.sv
View File

@@ -45,7 +45,11 @@ module taxi_eth_phy_25g_us_gt #
parameter logic GT_RX_PD = 1'b0,
parameter logic GT_RX_QPLL_SEL = 1'b0,
parameter logic GT_RX_LPM_EN = 1'b0,
parameter logic GT_RX_POLARITY = 1'b0
parameter logic GT_RX_POLARITY = 1'b0,
// MAC/PHY parameters
parameter DATA_W = 64,
parameter HDR_W = 2
)
(
input wire logic xcvr_ctrl_clk,
@@ -105,13 +109,18 @@ module taxi_eth_phy_25g_us_gt #
/*
* Serdes interface
*/
input wire logic [5:0] gt_txheader,
input wire logic [63:0] gt_txdata,
input wire logic gt_rxgearboxslip,
output wire logic [5:0] gt_rxheader,
output wire logic [1:0] gt_rxheadervalid,
output wire logic [63:0] gt_rxdata,
output wire logic [1:0] gt_rxdatavalid
input wire logic [DATA_W-1:0] serdes_tx_data,
input wire logic serdes_tx_data_valid,
input wire logic [HDR_W-1:0] serdes_tx_hdr,
input wire logic serdes_tx_hdr_valid,
output wire logic serdes_tx_gbx_req_start,
output wire logic serdes_tx_gbx_req_stall,
input wire logic serdes_tx_gbx_start,
output wire logic [DATA_W-1:0] serdes_rx_data,
output wire logic serdes_rx_data_valid,
output wire logic [HDR_W-1:0] serdes_rx_hdr,
output wire logic serdes_rx_hdr_valid,
input wire logic serdes_rx_bitslip
);
localparam GT_USP = FAMILY == "kintexuplus" || FAMILY == "virtexuplus" || FAMILY == "virtexuplusHBM"
@@ -340,6 +349,30 @@ gt_rx_reset_inst (
.rx_lpm_en_in(GT_RX_LPM_EN)
);
wire [6:0] gt_txsequence;
wire [5:0] gt_txheader;
wire [63:0] gt_txdata;
wire gt_rxgearboxslip;
wire [1:0] gt_rxstartofseq;
wire [5:0] gt_rxheader;
wire [1:0] gt_rxheadervalid;
wire [63:0] gt_rxdata;
wire [1:0] gt_rxdatavalid;
assign gt_txdata = serdes_tx_data;
assign gt_txheader = {4'd0, serdes_tx_hdr};
assign gt_rxgearboxslip = serdes_rx_bitslip;
if (!SIM) begin
assign serdes_rx_data = gt_rxdata;
assign serdes_rx_data_valid = gt_rxdatavalid;
assign serdes_rx_hdr = gt_rxheader[1:0];
assign serdes_rx_hdr_valid = gt_rxheadervalid[0];
end
assign serdes_tx_gbx_req_start = 1'b0;
assign serdes_tx_gbx_req_stall = 1'b0;
if (SIM) begin : xcvr
// simulation (no GT core)
@@ -771,8 +804,8 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && !GT_USP) begin : xcvr
end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr
// UltraScale/UltraScale+ GTY (channel only)
taxi_eth_phy_25g_us_gty_channel
taxi_eth_phy_25g_us_gty_channel_inst (
taxi_eth_phy_25g_us_gty_ch
taxi_eth_phy_25g_us_gty_ch_inst (
// Common
.gtpowergood_out(xcvr_gtpowergood_out),
@@ -864,8 +897,8 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr
end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr
// UltraScale/UltraScale+ GTY (channel only)
taxi_eth_phy_25g_us_gth_channel
taxi_eth_phy_25g_us_gth_channel_inst (
taxi_eth_phy_25g_us_gth_ch
taxi_eth_phy_25g_us_gth_ch_inst (
// Common
.gtpowergood_out(xcvr_gtpowergood_out),

6
src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.f Normal file
View File

@@ -0,0 +1,6 @@
taxi_eth_phy_25g_us_gt_ll.sv
../../lib/taxi/src/sync/rtl/taxi_sync_reset.sv
../../lib/taxi/src/sync/rtl/taxi_sync_signal.sv
../../lib/taxi/src/hip/rtl/us/taxi_gt_qpll_reset.sv
../../lib/taxi/src/hip/rtl/us/taxi_gt_rx_reset.sv
../../lib/taxi/src/hip/rtl/us/taxi_gt_tx_reset.sv

1127
src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.sv Normal file
View File

File diff suppressed because it is too large Load Diff

34
src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl
View File

@@ -35,8 +35,8 @@ if {[string first uplus [get_property FAMILY [get_property PART [current_project
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
}
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
# channel power down
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
# channel clock selection
@@ -91,6 +91,14 @@ proc create_gtwizard_ip {name preset config} {
set_property -dict $config_list $ip
}
# normal latency (async gearbox)
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
dict set config TX_BUFFER_MODE {1}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B_ASYNC}
dict set config RX_BUFFER_MODE {1}
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
@@ -101,4 +109,24 @@ create_gtwizard_ip "${base_name}_full" $preset $config
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_channel" $preset $config
create_gtwizard_ip "${base_name}_ch" $preset $config
# low latency (async gearbox with buffer bypass)
dict set config TX_DATA_ENCODING {64B66B}
dict set config TX_BUFFER_MODE {0}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B}
dict set config RX_BUFFER_MODE {0}
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
create_gtwizard_ip "${base_name}_ll_full" $preset $config
# variant with channel only
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_ll_ch" $preset $config

34
src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_161.tcl
View File

@@ -35,8 +35,8 @@ if {[string first uplus [get_property FAMILY [get_property PART [current_project
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
}
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
# channel power down
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
# channel clock selection
@@ -91,6 +91,14 @@ proc create_gtwizard_ip {name preset config} {
set_property -dict $config_list $ip
}
# normal latency (async gearbox)
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
dict set config TX_BUFFER_MODE {1}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B_ASYNC}
dict set config RX_BUFFER_MODE {1}
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
@@ -101,4 +109,24 @@ create_gtwizard_ip "${base_name}_full" $preset $config
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_channel" $preset $config
create_gtwizard_ip "${base_name}_ch" $preset $config
# low latency (async gearbox with buffer bypass)
dict set config TX_DATA_ENCODING {64B66B}
dict set config TX_BUFFER_MODE {0}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B}
dict set config RX_BUFFER_MODE {0}
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
create_gtwizard_ip "${base_name}_ll_full" $preset $config
# variant with channel only
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_ll_ch" $preset $config

34
src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_322.tcl
View File

@@ -35,8 +35,8 @@ if {[string first uplus [get_property FAMILY [get_property PART [current_project
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
}
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
# channel power down
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
# channel clock selection
@@ -91,6 +91,14 @@ proc create_gtwizard_ip {name preset config} {
set_property -dict $config_list $ip
}
# normal latency (async gearbox)
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
dict set config TX_BUFFER_MODE {1}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B_ASYNC}
dict set config RX_BUFFER_MODE {1}
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
@@ -101,4 +109,24 @@ create_gtwizard_ip "${base_name}_full" $preset $config
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_channel" $preset $config
create_gtwizard_ip "${base_name}_ch" $preset $config
# low latency (async gearbox with buffer bypass)
dict set config TX_DATA_ENCODING {64B66B}
dict set config TX_BUFFER_MODE {0}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B}
dict set config RX_BUFFER_MODE {0}
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
create_gtwizard_ip "${base_name}_ll_full" $preset $config
# variant with channel only
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_ll_ch" $preset $config

34
src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl
View File

@@ -35,8 +35,8 @@ if {[string first uplus [get_property FAMILY [get_property PART [current_project
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
}
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
# channel power down
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
# channel clock selection
@@ -91,6 +91,14 @@ proc create_gtwizard_ip {name preset config} {
set_property -dict $config_list $ip
}
# normal latency (async gearbox)
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
dict set config TX_BUFFER_MODE {1}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B_ASYNC}
dict set config RX_BUFFER_MODE {1}
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
@@ -101,4 +109,24 @@ create_gtwizard_ip "${base_name}_full" $preset $config
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_channel" $preset $config
create_gtwizard_ip "${base_name}_ch" $preset $config
# low latency (async gearbox with buffer bypass)
dict set config TX_DATA_ENCODING {64B66B}
dict set config TX_BUFFER_MODE {0}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B}
dict set config RX_BUFFER_MODE {0}
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
create_gtwizard_ip "${base_name}_ll_full" $preset $config
# variant with channel only
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_ll_ch" $preset $config

34
src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl
View File

@@ -35,8 +35,8 @@ if {[string first uplus [get_property FAMILY [get_property PART [current_project
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
}
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
# channel power down
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
# channel clock selection
@@ -91,6 +91,14 @@ proc create_gtwizard_ip {name preset config} {
set_property -dict $config_list $ip
}
# normal latency (async gearbox)
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
dict set config TX_BUFFER_MODE {1}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B_ASYNC}
dict set config RX_BUFFER_MODE {1}
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
@@ -101,4 +109,24 @@ create_gtwizard_ip "${base_name}_full" $preset $config
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_channel" $preset $config
create_gtwizard_ip "${base_name}_ch" $preset $config
# low latency (async gearbox with buffer bypass)
dict set config TX_DATA_ENCODING {64B66B}
dict set config TX_BUFFER_MODE {0}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B}
dict set config RX_BUFFER_MODE {0}
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
create_gtwizard_ip "${base_name}_ll_full" $preset $config
# variant with channel only
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_ll_ch" $preset $config

34
src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_322.tcl
View File

@@ -35,8 +35,8 @@ if {[string first uplus [get_property FAMILY [get_property PART [current_project
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
}
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
# channel power down
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
# channel clock selection
@@ -91,6 +91,14 @@ proc create_gtwizard_ip {name preset config} {
set_property -dict $config_list $ip
}
# normal latency (async gearbox)
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
dict set config TX_BUFFER_MODE {1}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B_ASYNC}
dict set config RX_BUFFER_MODE {1}
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
@@ -101,4 +109,24 @@ create_gtwizard_ip "${base_name}_full" $preset $config
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_channel" $preset $config
create_gtwizard_ip "${base_name}_ch" $preset $config
# low latency (async gearbox with buffer bypass)
dict set config TX_DATA_ENCODING {64B66B}
dict set config TX_BUFFER_MODE {0}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B}
dict set config RX_BUFFER_MODE {0}
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
create_gtwizard_ip "${base_name}_ll_full" $preset $config
# variant with channel only
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_ll_ch" $preset $config

34
src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl
View File

@@ -35,8 +35,8 @@ if {[string first uplus [get_property FAMILY [get_property PART [current_project
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
}
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
# channel power down
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
# channel clock selection
@@ -91,6 +91,14 @@ proc create_gtwizard_ip {name preset config} {
set_property -dict $config_list $ip
}
# normal latency (async gearbox)
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
dict set config TX_BUFFER_MODE {1}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B_ASYNC}
dict set config RX_BUFFER_MODE {1}
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
@@ -101,4 +109,24 @@ create_gtwizard_ip "${base_name}_full" $preset $config
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_channel" $preset $config
create_gtwizard_ip "${base_name}_ch" $preset $config
# low latency (async gearbox with buffer bypass)
dict set config TX_DATA_ENCODING {64B66B}
dict set config TX_BUFFER_MODE {0}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B}
dict set config RX_BUFFER_MODE {0}
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
create_gtwizard_ip "${base_name}_ll_full" $preset $config
# variant with channel only
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_ll_ch" $preset $config

34
src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl
View File

@@ -35,8 +35,8 @@ if {[string first uplus [get_property FAMILY [get_property PART [current_project
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
}
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
# channel power down
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
# channel clock selection
@@ -91,6 +91,14 @@ proc create_gtwizard_ip {name preset config} {
set_property -dict $config_list $ip
}
# normal latency (async gearbox)
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
dict set config TX_BUFFER_MODE {1}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B_ASYNC}
dict set config RX_BUFFER_MODE {1}
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
@@ -101,4 +109,24 @@ create_gtwizard_ip "${base_name}_full" $preset $config
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_channel" $preset $config
create_gtwizard_ip "${base_name}_ch" $preset $config
# low latency (async gearbox with buffer bypass)
dict set config TX_DATA_ENCODING {64B66B}
dict set config TX_BUFFER_MODE {0}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B}
dict set config RX_BUFFER_MODE {0}
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
create_gtwizard_ip "${base_name}_ll_full" $preset $config
# variant with channel only
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_ll_ch" $preset $config

34
src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_322.tcl
View File

@@ -35,8 +35,8 @@ if {[string first uplus [get_property FAMILY [get_property PART [current_project
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
}
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
# channel power down
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
# channel clock selection
@@ -91,6 +91,14 @@ proc create_gtwizard_ip {name preset config} {
set_property -dict $config_list $ip
}
# normal latency (async gearbox)
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
dict set config TX_BUFFER_MODE {1}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B_ASYNC}
dict set config RX_BUFFER_MODE {1}
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
@@ -101,4 +109,24 @@ create_gtwizard_ip "${base_name}_full" $preset $config
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_channel" $preset $config
create_gtwizard_ip "${base_name}_ch" $preset $config
# low latency (async gearbox with buffer bypass)
dict set config TX_DATA_ENCODING {64B66B}
dict set config TX_BUFFER_MODE {0}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B}
dict set config RX_BUFFER_MODE {0}
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
create_gtwizard_ip "${base_name}_ll_full" $preset $config
# variant with channel only
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_ll_ch" $preset $config