eth: Add support for synchronous gearbox to PHY, MAC+PHY, and GT wrappers
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
@@ -24,19 +24,24 @@ from cocotbext.eth import XgmiiFrame
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class BaseRSerdesSource():
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def __init__(self, data, hdr, clock, enable=None, slip=None, scramble=True, reverse=False, *args, **kwargs):
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def __init__(self, data, hdr, clock, enable=None, slip=None, data_valid=None, hdr_valid=None,
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gbx_start=None, scramble=True, reverse=False, gbx_cfg=None, *args, **kwargs):
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self.log = logging.getLogger(f"cocotb.{data._path}")
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self.data = data
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self.hdr = hdr
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self.clock = clock
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self.enable = enable
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self.slip = slip
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self.data_valid = data_valid
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self.hdr_valid = hdr_valid
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self.gbx_start = gbx_start
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self.scramble = scramble
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self.reverse = reverse
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self.log.info("BASE-R serdes source")
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self.log.info("Copyright (c) 2021 Alex Forencich")
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self.log.info("https://github.com/alexforencich/verilog-ethernet")
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self.log.info("Copyright (c) 2021-2025 FPGA Ninja, LLC")
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self.log.info("https://github.com/fpganinja/taxi")
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super().__init__(*args, **kwargs)
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@@ -53,6 +58,13 @@ class BaseRSerdesSource():
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self.bit_offset = 0
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self.gbx_seq = 0
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self.gbx_seq_len = None
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self.gbx_seq_stall = None
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self.gbx_in_bits = 66
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self.gbx_out_bits = 66
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self.gbx_bit_cnt = 0
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self.queue_occupancy_bytes = 0
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self.queue_occupancy_frames = 0
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@@ -71,11 +83,64 @@ class BaseRSerdesSource():
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self.log.info(" Enable scrambler: %s", self.scramble)
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self.log.info(" Bit reverse: %s", self.reverse)
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if gbx_cfg:
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self.set_gbx_cfg(*gbx_cfg)
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self.data.setimmediatevalue(0)
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if self.data_valid is not None:
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self.data_valid.setimmediatevalue(0)
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self.hdr.setimmediatevalue(0)
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if self.hdr_valid is not None:
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self.hdr_valid.setimmediatevalue(0)
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if self.gbx_start is not None:
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self.gbx_start.setimmediatevalue(0)
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self._run_cr = cocotb.start_soon(self._run())
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def set_gbx_cfg(self, seq_len=None, seq_stall=None):
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self.log.info("Set gearbox configuration")
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if seq_len is None:
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self.log.info("Gearbox disabled")
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self.gbx_bit_cnt = 0
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self.gbx_seq_len = None
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self.gbx_seq_stall = None
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self.gbx_in_bits = 66
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self.gbx_out_bits = 66
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self.gbx_seq = 0
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seq_stall = sorted(list(set(seq_stall)))
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for x in seq_stall:
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assert 0 <= x < seq_len
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self.log.info(" Sequence length: %d cycles", seq_len)
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self.log.info(" Stall cycles: %s", seq_stall)
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out_bits = 66
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in_cycles = seq_len
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out_cycles = in_cycles - len(seq_stall)
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in_bits = (out_bits * out_cycles) // in_cycles
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self.log.info(" Input: %d bits (%d cycles)", in_bits, in_cycles)
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self.log.info(" Output: %d bits (%d cycles)", out_bits, out_cycles)
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self.log.info(" Gearbox ratio: %d:%d", in_bits, out_bits)
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assert in_cycles*in_bits == out_cycles*out_bits
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self.gbx_seq = 0
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self.gbx_seq_len = seq_len
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self.gbx_seq_stall = set(seq_stall)
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self.gbx_in_bits = in_bits
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self.gbx_out_bits = out_bits
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self.gbx_bit_cnt = 0
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for k in range(self.gbx_seq_len):
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self.gbx_bit_cnt += in_bits
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if k in self.gbx_seq_stall:
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continue
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self.gbx_bit_cnt = max(self.gbx_bit_cnt - out_bits, 0)
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async def send(self, frame):
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while self.full():
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self.dequeue_event.clear()
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@@ -134,13 +199,52 @@ class BaseRSerdesSource():
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last_d = 0
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self.active = False
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clk_period = 0
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last_clk = 0
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gbx_delay = 0
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while True:
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await RisingEdge(self.clock)
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if not clk_period:
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if last_clk:
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clk_period = get_sim_time() - last_clk
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else:
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last_clk = get_sim_time()
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# clock enable
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if self.enable is not None and not self.enable.value:
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continue
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# gearbox sequence
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if self.gbx_seq_len:
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self.gbx_seq = (self.gbx_seq + 1) % self.gbx_seq_len
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if self.gbx_start is not None:
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self.gbx_start.value = (self.gbx_seq == 0)
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self.gbx_bit_cnt += self.gbx_in_bits
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# stall cycle
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if self.gbx_seq in self.gbx_seq_stall:
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self.data.value = 0
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if self.data_valid is not None:
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self.data_valid.value = 0
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self.hdr.value = 0
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if self.hdr_valid is not None:
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self.hdr_valid.value = 0
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continue
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self.gbx_bit_cnt = max(self.gbx_bit_cnt - self.gbx_out_bits, 0)
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gbx_delay = (self.gbx_bit_cnt * clk_period) // self.gbx_in_bits
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else:
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self.gbx_seq = 0
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self.gbx_bit_cnt = 0
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gbx_delay = 0
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if self.gbx_start is not None:
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self.gbx_start.value = 0
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if ifg_cnt + deficit_idle_cnt > self.byte_lanes-1 or (not self.enable_dic and ifg_cnt > 4):
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# in IFG
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ifg_cnt = ifg_cnt - self.byte_lanes
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@@ -158,7 +262,7 @@ class BaseRSerdesSource():
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self.queue_occupancy_bytes -= len(frame)
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self.queue_occupancy_frames -= 1
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self.current_frame = frame
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frame.sim_time_start = get_sim_time()
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frame.sim_time_start = get_sim_time() - gbx_delay
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frame.sim_time_sfd = None
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frame.sim_time_end = None
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self.log.info("TX frame: %s", frame)
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@@ -201,14 +305,14 @@ class BaseRSerdesSource():
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if frame is not None:
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d = frame.data[frame_offset]
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if frame.sim_time_sfd is None and d == EthPre.SFD:
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frame.sim_time_sfd = get_sim_time()
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frame.sim_time_sfd = get_sim_time() - gbx_delay
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dl.append(d)
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cl.append(frame.ctrl[frame_offset])
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frame_offset += 1
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if frame_offset >= len(frame.data):
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ifg_cnt = max(self.ifg - (self.byte_lanes-k), 0)
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frame.sim_time_end = get_sim_time()
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frame.sim_time_end = get_sim_time() - gbx_delay
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frame.handle_tx_complete()
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frame = None
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self.current_frame = None
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@@ -349,23 +453,35 @@ class BaseRSerdesSource():
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hdr = sum(1 << (1-i) for i in range(2) if (hdr >> i) & 1)
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self.data.value = data
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if self.data_valid is not None:
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self.data_valid.value = 1
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self.hdr.value = hdr
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if self.hdr_valid is not None:
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self.hdr_valid.value = 1
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class BaseRSerdesSink:
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def __init__(self, data, hdr, clock, enable=None, scramble=True, reverse=False, *args, **kwargs):
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def __init__(self, data, hdr, clock, enable=None, data_valid=None, hdr_valid=None,
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gbx_req_start=None, gbx_req_stall=None, gbx_start=None,
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scramble=True, reverse=False, gbx_cfg=None, *args, **kwargs):
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self.log = logging.getLogger(f"cocotb.{data._path}")
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self.data = data
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self.hdr = hdr
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self.clock = clock
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self.enable = enable
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self.data_valid = data_valid
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self.hdr_valid = hdr_valid
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self.gbx_req_start = gbx_req_start
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self.gbx_req_stall = gbx_req_stall
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self.gbx_start = gbx_start
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self.scramble = scramble
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self.reverse = reverse
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self.log.info("BASE-R serdes sink")
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self.log.info("Copyright (c) 2021 Alex Forencich")
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self.log.info("https://github.com/alexforencich/verilog-ethernet")
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self.log.info("Copyright (c) 2021-2025 FPGA Ninja, LLC")
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self.log.info("https://github.com/fpganinja/taxi")
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super().__init__(*args, **kwargs)
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@@ -373,6 +489,14 @@ class BaseRSerdesSink:
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self.queue = Queue()
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self.active_event = Event()
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self.gbx_seq = 0
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self.gbx_seq_gen = 0
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self.gbx_seq_len = None
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self.gbx_seq_stall = None
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self.gbx_in_bits = 66
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self.gbx_out_bits = 66
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self.gbx_bit_cnt = 0
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self.queue_occupancy_bytes = 0
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self.queue_occupancy_frames = 0
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@@ -388,8 +512,57 @@ class BaseRSerdesSink:
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self.log.info(" Enable scrambler: %s", self.scramble)
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self.log.info(" Bit reverse: %s", self.reverse)
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if gbx_cfg:
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self.set_gbx_cfg(*gbx_cfg)
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if self.gbx_req_start is not None:
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self.gbx_req_start.setimmediatevalue(0)
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if self.gbx_req_stall is not None:
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self.gbx_req_stall.setimmediatevalue(0)
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self._run_cr = cocotb.start_soon(self._run())
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def set_gbx_cfg(self, seq_len=None, seq_stall=None):
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self.log.info("Set gearbox configuration")
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if seq_len is None:
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self.log.info("Gearbox disabled")
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self.gbx_seq_len = None
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self.gbx_seq_stall = None
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seq_stall = sorted(list(set(seq_stall)))
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for x in seq_stall:
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assert 0 <= x < seq_len
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self.log.info(" Sequence length: %d cycles", seq_len)
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self.log.info(" Stall cycles: %s", seq_stall)
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in_bits = 66
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out_cycles = seq_len
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in_cycles = out_cycles - len(seq_stall)
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out_bits = (in_bits * in_cycles) // out_cycles
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self.log.info(" Input: %d bits (%d cycles)", in_bits, in_cycles)
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self.log.info(" Output: %d bits (%d cycles)", out_bits, out_cycles)
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self.log.info(" Gearbox ratio: %d:%d", in_bits, out_bits)
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assert in_cycles*in_bits == out_cycles*out_bits
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self.gbx_seq = 0
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self.gbx_seq_gen = 0
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self.gbx_seq_len = seq_len
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self.gbx_seq_stall = set(seq_stall)
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self.gbx_in_bits = in_bits
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self.gbx_out_bits = out_bits
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self.gbx_bit_cnt = 0
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for k in range(self.gbx_seq_len):
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self.gbx_bit_cnt = max(self.gbx_bit_cnt - out_bits, 0)
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if k in self.gbx_seq_stall:
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continue
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self.gbx_bit_cnt += in_bits
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def _recv(self, frame, compact=True):
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if self.queue.empty():
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self.active_event.clear()
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@@ -436,13 +609,69 @@ class BaseRSerdesSink:
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scrambler_state = 0
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self.active = False
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clk_period = 0
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last_clk = 0
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gbx_delay = 0
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sync_bad = True
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while True:
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await RisingEdge(self.clock)
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if not clk_period:
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if last_clk:
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clk_period = get_sim_time() - last_clk
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else:
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last_clk = get_sim_time()
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# clock enable
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if self.enable is not None and not self.enable.value:
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continue
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# gearbox sequence
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if self.gbx_seq_len:
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# generation
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self.gbx_seq_gen = (self.gbx_seq_gen + 1) % self.gbx_seq_len
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if self.gbx_req_start is not None:
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self.gbx_req_start.value = (self.gbx_seq_gen == 0)
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# stall cycle
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if self.gbx_req_stall is not None:
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self.gbx_req_stall.value = (self.gbx_seq_gen in self.gbx_seq_stall)
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# sync
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self.gbx_seq = (self.gbx_seq + 1) % self.gbx_seq_len
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if self.gbx_start is not None:
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if self.gbx_start.value.integer:
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self.gbx_seq = 0
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self.gbx_bit_cnt = max(self.gbx_bit_cnt - self.gbx_out_bits, 0)
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if self.gbx_seq in self.gbx_seq_stall:
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continue
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self.gbx_bit_cnt += self.gbx_in_bits
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gbx_delay = (self.gbx_bit_cnt * clk_period) // self.gbx_out_bits
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else:
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self.gbx_seq = 0
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self.gbx_seq_gen = 0
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self.gbx_bit_cnt = 0
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gbx_delay = 0
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if self.gbx_start is not None:
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self.gbx_start.value = 1
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if self.data_valid is not None:
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if not self.data_valid.value.integer:
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# stall
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if self.gbx_seq_len and not sync_bad:
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sync_bad = True
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self.log.warning("Data not valid outside of gearbox stall cycle")
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continue
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sync_bad = False
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data = self.data.value.integer
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hdr = self.hdr.value.integer
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@@ -590,7 +819,7 @@ class BaseRSerdesSink:
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if c_val and d_val == XgmiiCtrl.START:
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# start
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frame = XgmiiFrame(bytearray([EthPre.PRE]), [0])
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frame.sim_time_start = get_sim_time()
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frame.sim_time_start = get_sim_time() + gbx_delay
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frame.start_lane = offset
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else:
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if c_val:
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@@ -601,7 +830,7 @@ class BaseRSerdesSink:
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frame.ctrl.append(c_val)
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frame.compact()
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frame.sim_time_end = get_sim_time()
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frame.sim_time_end = get_sim_time() + gbx_delay
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self.log.info("RX frame: %s", frame)
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self.queue_occupancy_bytes += len(frame)
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@@ -613,7 +842,7 @@ class BaseRSerdesSink:
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frame = None
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else:
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if frame.sim_time_sfd is None and d_val == EthPre.SFD:
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frame.sim_time_sfd = get_sim_time()
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frame.sim_time_sfd = get_sim_time() + gbx_delay
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frame.data.append(d_val)
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frame.ctrl.append(c_val)
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