Alex Forencich
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17e48c5f51
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eth: Support 32-bit mode in UltraScale wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-15 13:16:58 -07:00 |
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Alex Forencich
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2e1619a045
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eth: Connect and tie off txsequence
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-15 01:20:23 -07:00 |
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Alex Forencich
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e993a6cfbf
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eth: Cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-13 19:38:06 -07:00 |
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Alex Forencich
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65eef8b5e8
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eth: Parameter cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-13 19:28:21 -07:00 |
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Alex Forencich
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f9041cd9d2
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eth: Fix multidriven net
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-13 16:51:07 -07:00 |
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Alex Forencich
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e846e7f0cd
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eth: Add gearbox support to 64-bit 10G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-13 16:39:55 -07:00 |
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Alex Forencich
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0fd4000f69
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eth: Support both split and combined MAC/PCS in UltraScale wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-13 14:31:14 -07:00 |
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Alex Forencich
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4e66dd0f98
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eth: Rename gearbox start signals to sync
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-12 15:45:07 -07:00 |
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Alex Forencich
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ca3ee2d197
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eth: Fix PFC/LFC parameters in 25G MAC modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-12 14:56:55 -07:00 |
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Alex Forencich
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e4762b7a8c
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eth: Add support for synchronous gearbox to PHY, MAC+PHY, and GT wrappers
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-05-30 21:14:54 -07:00 |
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Alex Forencich
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8a77ee9fc7
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eth: Add reset logic, QPLL control signals, and additional configuration parameters for US/US+ GTH/GTY transceivers
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-05-21 21:06:45 -07:00 |
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Alex Forencich
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66b53d98a2
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Reorganize repository
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-05-18 12:25:59 -07:00 |
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