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a86f8581161f15029d92db00bf6a9d1f6af35767
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3 Commits

Author SHA1 Message Date
Alex Forencich
84fb93b5c3 example: Add signal sync timing constraints to example designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-02-25 16:04:32 -08:00
Alex Forencich
db8b1fc27e example/VCU108: Add 25G MACs on QSFP28 port on VCU108 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-02-22 22:33:54 -08:00
Alex Forencich
c7b79f9afb example/VCU108: Add example design for VCU108 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-02-18 15:14:36 -08:00