Alex Forencich
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4da6771603
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dma: Prevent width-related warnings when optional AXI stream sideband signals are not used
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-12-31 13:02:26 -08:00 |
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Alex Forencich
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bfb96c677a
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dma: Add DMA interface mux modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-12-23 18:02:19 -08:00 |
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Alex Forencich
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2ada85105f
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dma: Add DMA RAM demux modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-12-23 18:01:57 -08:00 |
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Alex Forencich
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9d8c5fce73
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dma: Add DMA descriptor mux module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-12-23 18:01:40 -08:00 |
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Alex Forencich
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008e06ff48
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dma: Cast RAM address width appropriately
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-12-15 20:53:15 -08:00 |
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Alex Forencich
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ec00c2323c
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dma: Cast PCIe TLP tag width appropriately
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-12-15 20:22:29 -08:00 |
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Alex Forencich
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cb3538a0de
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dma: Add interface configuration checks to DMA PSDPRAM module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-12-15 20:21:24 -08:00 |
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Alex Forencich
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cbe0fa730d
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dma: Add missing ASID signals to DMA descriptor interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-12-15 20:12:42 -08:00 |
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Alex Forencich
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004246608e
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Use logic instead of reg
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-07 02:14:19 -08:00 |
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Alex Forencich
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5f814e7da8
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Clean up always blocks
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-07 01:51:18 -08:00 |
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Alex Forencich
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3b95e2f279
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dma: Remove unnecessary handshake condition
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-04 17:45:54 -08:00 |
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Alex Forencich
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b0dd91aa8d
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dma: Add UltraScale PCIe DMA interface module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-04 17:18:26 -08:00 |
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Alex Forencich
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14d988d1f2
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dma: Add AXI DMA interface module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-04 12:41:07 -08:00 |
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Alex Forencich
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851919f16f
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dma: Add AXI stream sink DMA client module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-03 21:30:55 -08:00 |
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Alex Forencich
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5663572421
|
dma: Add AXI stream source DMA client module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-03 21:30:20 -08:00 |
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Alex Forencich
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5b0c83fc57
|
dma: Add AXI streaming DMA module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-03 17:14:24 -08:00 |
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Alex Forencich
|
9442bb7fbb
|
dma: Add AXI central DMA module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-03 11:42:04 -08:00 |
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Alex Forencich
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4b7e3d066d
|
dma: Add SV interface for DMA descriptors
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-03 09:23:46 -08:00 |
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Alex Forencich
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32ed95893c
|
dma: Clean up casts in DMA PSDPRAM model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-07 14:37:41 -07:00 |
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Alex Forencich
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40908b1b92
|
Testbench cleanup for cocotb 2.0
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-07 10:59:38 -07:00 |
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Alex Forencich
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a6db298eeb
|
dma: Add async DMA PSDPRAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-31 21:30:25 -07:00 |
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Alex Forencich
|
48da5315fe
|
dma: Add DMA PSDPRAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-31 21:29:55 -07:00 |
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Alex Forencich
|
d57b49b29c
|
dma: Add PSDPRAM simulation model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-31 21:05:20 -07:00 |
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Alex Forencich
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c5fea4d920
|
dma: Add lib symlink
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-31 21:04:44 -07:00 |
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Alex Forencich
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10500e6c6c
|
dma: Add DMA RAM interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-31 21:04:22 -07:00 |
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