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115bacae026afb21474bee62ee58a1afeca8d8cc
taxi-bsl
/
example
/
KC705
/
fpga
/
fpga_sgmii_1g
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Alex Forencich
84fb93b5c3
example: Add signal sync timing constraints to example designs
...
Signed-off-by: Alex Forencich <
alex@alexforencich.com
>
2025-02-25 16:04:32 -08:00
..
config.tcl
example/KC705: Add example design for Xilinx KC705
2025-02-18 09:45:36 -08:00
Makefile
example: Add signal sync timing constraints to example designs
2025-02-25 16:04:32 -08:00
