466 lines
13 KiB
Systemverilog
466 lines
13 KiB
Systemverilog
// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2021-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga #
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(
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parameter logic SIM = 1'b0,
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parameter string VENDOR = "XILINX",
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parameter string FAMILY = "virtexuplus"
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)
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(
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/*
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* Clock: 200 MHz LVDS
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*/
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input wire logic ref_clk_p,
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input wire logic ref_clk_n,
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/*
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* GPIO
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*/
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input wire logic [1:0] btn,
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input wire logic [7:0] sw,
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output wire logic [7:0] led,
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/*
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* I2C for board management
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*/
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inout wire logic i2c_main_scl,
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inout wire logic i2c_main_sda,
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output wire logic i2c_main_rst_n,
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/*
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* PLL
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*/
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output wire logic clk_gty2_fdec,
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output wire logic clk_gty2_finc,
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input wire logic clk_gty2_intr_n,
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input wire logic clk_gty2_lol_n,
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output wire logic clk_gty2_oe_n,
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output wire logic clk_gty2_sync_n,
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output wire logic clk_gty2_rst_n,
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/*
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* UART: 921600 bps, 8N1
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*/
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output wire logic uart_rxd,
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input wire logic uart_txd,
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input wire logic uart_rts,
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output wire logic uart_cts,
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output wire logic uart_rst_n,
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output wire logic uart_suspend_n,
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/*
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* Ethernet: QSFP28
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*/
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output wire logic qsfp_1_tx_p[4],
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output wire logic qsfp_1_tx_n[4],
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input wire logic qsfp_1_rx_p[4],
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input wire logic qsfp_1_rx_n[4],
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input wire logic qsfp_1_mgt_refclk_p,
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input wire logic qsfp_1_mgt_refclk_n,
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output wire logic qsfp_1_resetl,
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input wire logic qsfp_1_modprsl,
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input wire logic qsfp_1_intl,
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output wire logic qsfp_2_tx_p[4],
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output wire logic qsfp_2_tx_n[4],
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input wire logic qsfp_2_rx_p[4],
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input wire logic qsfp_2_rx_n[4],
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input wire logic qsfp_2_mgt_refclk_p,
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input wire logic qsfp_2_mgt_refclk_n,
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output wire logic qsfp_2_resetl,
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input wire logic qsfp_2_modprsl,
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input wire logic qsfp_2_intl,
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output wire logic qsfp_3_tx_p[4],
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output wire logic qsfp_3_tx_n[4],
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input wire logic qsfp_3_rx_p[4],
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input wire logic qsfp_3_rx_n[4],
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input wire logic qsfp_3_mgt_refclk_p,
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input wire logic qsfp_3_mgt_refclk_n,
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output wire logic qsfp_3_resetl,
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input wire logic qsfp_3_modprsl,
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input wire logic qsfp_3_intl,
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output wire logic qsfp_4_tx_p[4],
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output wire logic qsfp_4_tx_n[4],
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input wire logic qsfp_4_rx_p[4],
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input wire logic qsfp_4_rx_n[4],
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input wire logic qsfp_4_mgt_refclk_p,
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input wire logic qsfp_4_mgt_refclk_n,
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output wire logic qsfp_4_resetl,
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input wire logic qsfp_4_modprsl,
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input wire logic qsfp_4_intl,
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output wire logic qsfp_5_tx_p[4],
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output wire logic qsfp_5_tx_n[4],
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input wire logic qsfp_5_rx_p[4],
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input wire logic qsfp_5_rx_n[4],
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input wire logic qsfp_5_mgt_refclk_p,
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input wire logic qsfp_5_mgt_refclk_n,
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output wire logic qsfp_5_resetl,
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input wire logic qsfp_5_modprsl,
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input wire logic qsfp_5_intl,
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output wire logic qsfp_6_tx_p[4],
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output wire logic qsfp_6_tx_n[4],
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input wire logic qsfp_6_rx_p[4],
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input wire logic qsfp_6_rx_n[4],
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input wire logic qsfp_6_mgt_refclk_p,
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input wire logic qsfp_6_mgt_refclk_n,
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output wire logic qsfp_6_resetl,
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input wire logic qsfp_6_modprsl,
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input wire logic qsfp_6_intl,
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output wire logic qsfp_7_tx_p[4],
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output wire logic qsfp_7_tx_n[4],
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input wire logic qsfp_7_rx_p[4],
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input wire logic qsfp_7_rx_n[4],
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input wire logic qsfp_7_mgt_refclk_p,
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input wire logic qsfp_7_mgt_refclk_n,
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output wire logic qsfp_7_resetl,
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input wire logic qsfp_7_modprsl,
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input wire logic qsfp_7_intl,
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output wire logic qsfp_8_tx_p[4],
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output wire logic qsfp_8_tx_n[4],
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input wire logic qsfp_8_rx_p[4],
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input wire logic qsfp_8_rx_n[4],
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input wire logic qsfp_8_mgt_refclk_p,
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input wire logic qsfp_8_mgt_refclk_n,
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output wire logic qsfp_8_resetl,
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input wire logic qsfp_8_modprsl,
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input wire logic qsfp_8_intl,
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output wire logic qsfp_9_tx_p[4],
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output wire logic qsfp_9_tx_n[4],
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input wire logic qsfp_9_rx_p[4],
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input wire logic qsfp_9_rx_n[4],
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input wire logic qsfp_9_mgt_refclk_p,
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input wire logic qsfp_9_mgt_refclk_n,
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output wire logic qsfp_9_resetl,
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input wire logic qsfp_9_modprsl,
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input wire logic qsfp_9_intl
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);
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// Clock and reset
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wire ref_clk_ibufg;
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// Internal 125 MHz clock
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wire clk_125mhz_mmcm_out;
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wire clk_125mhz_int;
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wire rst_125mhz_int;
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wire mmcm_rst = ~btn[0];
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wire mmcm_locked;
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wire mmcm_clkfb;
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IBUFGDS #(
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.DIFF_TERM("FALSE"),
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.IBUF_LOW_PWR("FALSE")
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)
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ref_clk_ibufg_inst (
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.O (ref_clk_ibufg),
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.I (ref_clk_p),
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.IB (ref_clk_n)
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);
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// MMCM instance
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MMCME4_BASE #(
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// 200 MHz input
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.CLKIN1_PERIOD(5.0),
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.REF_JITTER1(0.010),
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// 200 MHz input / 1 = 200 MHz PFD (range 10 MHz to 500 MHz)
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.DIVCLK_DIVIDE(1),
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// 200 MHz PFD * 5 = 1000 MHz VCO (range 800 MHz to 1600 MHz)
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.CLKFBOUT_MULT_F(5),
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.CLKFBOUT_PHASE(0),
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// 1000 MHz / 8 = 125 MHz, 0 degrees
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.CLKOUT0_DIVIDE_F(8),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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// Not used
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.CLKOUT1_DIVIDE(1),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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// Not used
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.CLKOUT2_DIVIDE(1),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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// Not used
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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// Not used
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT4_CASCADE("FALSE"),
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// Not used
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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// Not used
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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// optimized bandwidth
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.BANDWIDTH("OPTIMIZED"),
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// don't wait for lock during startup
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.STARTUP_WAIT("FALSE")
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)
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clk_mmcm_inst (
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// 200 MHz input
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.CLKIN1(ref_clk_ibufg),
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// direct clkfb feeback
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.CLKFBIN(mmcm_clkfb),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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// 125 MHz, 0 degrees
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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// Not used
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.CLKOUT1(),
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.CLKOUT1B(),
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// Not used
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.CLKOUT2(),
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.CLKOUT2B(),
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// Not used
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.CLKOUT3(),
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.CLKOUT3B(),
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// Not used
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.CLKOUT4(),
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// Not used
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.CLKOUT5(),
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// Not used
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.CLKOUT6(),
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// reset input
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.RST(mmcm_rst),
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// don't power down
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.PWRDWN(1'b0),
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// locked output
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_mmcm_out),
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.O(clk_125mhz_int)
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);
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taxi_sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~mmcm_locked),
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.out(rst_125mhz_int)
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);
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// GPIO
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wire btn_int;
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wire [7:0] sw_int;
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taxi_debounce_switch #(
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.WIDTH(9),
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.N(4),
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.RATE(125000)
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)
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debounce_switch_inst (
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.clk(clk_125mhz_int),
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.rst(rst_125mhz_int),
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.in({btn[1],
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sw}),
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.out({btn_int,
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sw_int})
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);
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wire uart_txd_int;
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wire uart_rts_int;
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taxi_sync_signal #(
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.WIDTH(2),
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.N(2)
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)
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sync_signal_inst (
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.clk(clk_125mhz_int),
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.in({uart_txd, uart_rts}),
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.out({uart_txd_int, uart_rts_int})
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);
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wire i2c_scl_i;
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wire i2c_scl_o;
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wire i2c_sda_i;
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wire i2c_sda_o;
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assign i2c_scl_i = i2c_main_scl;
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assign i2c_main_scl = i2c_scl_o ? 1'bz : 1'b0;
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assign i2c_sda_i = i2c_main_sda;
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assign i2c_main_sda = i2c_sda_o ? 1'bz : 1'b0;
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assign i2c_main_rst_n = 1'b1;
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localparam PORT_CNT = 9;
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localparam GTY_QUAD_CNT = PORT_CNT;
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localparam GTY_CNT = GTY_QUAD_CNT*4;
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localparam GTY_CLK_CNT = GTY_QUAD_CNT;
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wire eth_gty_tx_p[GTY_CNT];
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wire eth_gty_tx_n[GTY_CNT];
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wire eth_gty_rx_p[GTY_CNT];
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wire eth_gty_rx_n[GTY_CNT];
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wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
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wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
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wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
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assign clk_gty2_fdec = 1'b0;
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assign clk_gty2_finc = 1'b0;
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assign clk_gty2_oe_n = 1'b0;
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assign clk_gty2_sync_n = 1'b1;
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assign clk_gty2_rst_n = !rst_125mhz_int;
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wire eth_pll_locked = clk_gty2_lol_n;
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assign qsfp_1_tx_p = eth_gty_tx_p[4*0 +: 4];
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assign qsfp_1_tx_n = eth_gty_tx_n[4*0 +: 4];
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assign eth_gty_rx_p[4*0 +: 4] = qsfp_1_rx_p;
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assign eth_gty_rx_n[4*0 +: 4] = qsfp_1_rx_n;
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assign qsfp_2_tx_p = eth_gty_tx_p[4*1 +: 4];
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assign qsfp_2_tx_n = eth_gty_tx_n[4*1 +: 4];
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assign eth_gty_rx_p[4*1 +: 4] = qsfp_2_rx_p;
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assign eth_gty_rx_n[4*1 +: 4] = qsfp_2_rx_n;
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assign qsfp_3_tx_p = eth_gty_tx_p[4*2 +: 4];
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assign qsfp_3_tx_n = eth_gty_tx_n[4*2 +: 4];
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assign eth_gty_rx_p[4*2 +: 4] = qsfp_3_rx_p;
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assign eth_gty_rx_n[4*2 +: 4] = qsfp_3_rx_n;
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assign qsfp_4_tx_p = eth_gty_tx_p[4*3 +: 4];
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assign qsfp_4_tx_n = eth_gty_tx_n[4*3 +: 4];
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assign eth_gty_rx_p[4*3 +: 4] = qsfp_4_rx_p;
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assign eth_gty_rx_n[4*3 +: 4] = qsfp_4_rx_n;
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assign qsfp_5_tx_p = eth_gty_tx_p[4*4 +: 4];
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assign qsfp_5_tx_n = eth_gty_tx_n[4*4 +: 4];
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assign eth_gty_rx_p[4*4 +: 4] = qsfp_5_rx_p;
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assign eth_gty_rx_n[4*4 +: 4] = qsfp_5_rx_n;
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assign qsfp_6_tx_p = eth_gty_tx_p[4*5 +: 4];
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assign qsfp_6_tx_n = eth_gty_tx_n[4*5 +: 4];
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assign eth_gty_rx_p[4*5 +: 4] = qsfp_6_rx_p;
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assign eth_gty_rx_n[4*5 +: 4] = qsfp_6_rx_n;
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assign qsfp_7_tx_p = eth_gty_tx_p[4*6 +: 4];
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assign qsfp_7_tx_n = eth_gty_tx_n[4*6 +: 4];
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assign eth_gty_rx_p[4*6 +: 4] = qsfp_7_rx_p;
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assign eth_gty_rx_n[4*6 +: 4] = qsfp_7_rx_n;
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assign qsfp_8_tx_p = eth_gty_tx_p[4*7 +: 4];
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assign qsfp_8_tx_n = eth_gty_tx_n[4*7 +: 4];
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assign eth_gty_rx_p[4*7 +: 4] = qsfp_8_rx_p;
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assign eth_gty_rx_n[4*7 +: 4] = qsfp_8_rx_n;
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assign qsfp_9_tx_p = eth_gty_tx_p[4*8 +: 4];
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assign qsfp_9_tx_n = eth_gty_tx_n[4*8 +: 4];
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assign eth_gty_rx_p[4*8 +: 4] = qsfp_9_rx_p;
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assign eth_gty_rx_n[4*8 +: 4] = qsfp_9_rx_n;
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assign eth_gty_mgt_refclk_p[0] = qsfp_1_mgt_refclk_p;
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assign eth_gty_mgt_refclk_n[0] = qsfp_1_mgt_refclk_n;
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assign eth_gty_mgt_refclk_p[1] = qsfp_2_mgt_refclk_p;
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assign eth_gty_mgt_refclk_n[1] = qsfp_2_mgt_refclk_n;
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assign eth_gty_mgt_refclk_p[2] = qsfp_3_mgt_refclk_p;
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assign eth_gty_mgt_refclk_n[2] = qsfp_3_mgt_refclk_n;
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assign eth_gty_mgt_refclk_p[3] = qsfp_4_mgt_refclk_p;
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assign eth_gty_mgt_refclk_n[3] = qsfp_4_mgt_refclk_n;
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assign eth_gty_mgt_refclk_p[4] = qsfp_5_mgt_refclk_p;
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assign eth_gty_mgt_refclk_n[4] = qsfp_5_mgt_refclk_n;
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assign eth_gty_mgt_refclk_p[5] = qsfp_6_mgt_refclk_p;
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assign eth_gty_mgt_refclk_n[5] = qsfp_6_mgt_refclk_n;
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assign eth_gty_mgt_refclk_p[6] = qsfp_7_mgt_refclk_p;
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assign eth_gty_mgt_refclk_n[6] = qsfp_7_mgt_refclk_n;
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assign eth_gty_mgt_refclk_p[7] = qsfp_8_mgt_refclk_p;
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assign eth_gty_mgt_refclk_n[7] = qsfp_8_mgt_refclk_n;
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assign eth_gty_mgt_refclk_p[8] = qsfp_9_mgt_refclk_p;
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assign eth_gty_mgt_refclk_n[8] = qsfp_9_mgt_refclk_n;
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fpga_core #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.PORT_CNT(PORT_CNT),
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.GTY_QUAD_CNT(GTY_QUAD_CNT),
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.GTY_CNT(GTY_CNT),
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.GTY_CLK_CNT(GTY_CLK_CNT)
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)
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core_inst (
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/*
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* Clock: 125MHz
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* Synchronous reset
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*/
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.clk_125mhz(clk_125mhz_int),
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.rst_125mhz(rst_125mhz_int),
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/*
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* GPIO
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*/
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.btn(btn_int),
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.sw(sw_int),
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.led(led),
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/*
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* I2C for board management
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*/
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.i2c_scl_i(i2c_scl_i),
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.i2c_scl_o(i2c_scl_o),
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.i2c_sda_i(i2c_sda_i),
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.i2c_sda_o(i2c_sda_o),
|
|
|
|
/*
|
|
* UART: 921600 bps, 8N1
|
|
*/
|
|
.uart_rxd(uart_rxd),
|
|
.uart_txd(uart_txd_int),
|
|
.uart_rts(uart_rts_int),
|
|
.uart_cts(uart_cts),
|
|
.uart_rst_n(uart_rst_n),
|
|
.uart_suspend_n(uart_suspend_n),
|
|
|
|
/*
|
|
* Ethernet: QSFP28
|
|
*/
|
|
.eth_pll_locked(eth_pll_locked),
|
|
|
|
.eth_gty_tx_p(eth_gty_tx_p),
|
|
.eth_gty_tx_n(eth_gty_tx_n),
|
|
.eth_gty_rx_p(eth_gty_rx_p),
|
|
.eth_gty_rx_n(eth_gty_rx_n),
|
|
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
|
|
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
|
|
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
|
|
|
|
.eth_port_resetl({qsfp_9_resetl, qsfp_8_resetl, qsfp_7_resetl, qsfp_6_resetl, qsfp_5_resetl, qsfp_4_resetl, qsfp_3_resetl, qsfp_2_resetl, qsfp_1_resetl}),
|
|
.eth_port_modprsl({qsfp_9_modprsl, qsfp_8_modprsl, qsfp_7_modprsl, qsfp_6_modprsl, qsfp_5_modprsl, qsfp_4_modprsl, qsfp_3_modprsl, qsfp_2_modprsl, qsfp_1_modprsl}),
|
|
.eth_port_intl({qsfp_9_intl, qsfp_8_intl, qsfp_7_intl, qsfp_6_intl, qsfp_5_intl, qsfp_4_intl, qsfp_3_intl, qsfp_2_intl, qsfp_1_intl})
|
|
);
|
|
|
|
endmodule
|
|
|
|
`resetall
|