177 lines
3.1 KiB
Systemverilog
177 lines
3.1 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Zircon IP stack - RX ingress module
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*/
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module zircon_ip_rx_ingress #
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(
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parameter logic IPV6_EN = 1'b1,
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parameter logic HASH_EN = 1'b1
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* MAC interfaces
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*/
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input wire logic mac_rx_clk,
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input wire logic mac_rx_rst,
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taxi_axis_if.snk s_axis_mac_rx,
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/*
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* Internal interfaces
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*/
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taxi_axis_if.src m_axis_pkt,
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taxi_axis_if.src m_axis_meta_hdr,
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taxi_axis_if.src m_axis_meta_len
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);
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localparam MAC_DATA_W = s_axis_mac_rx.DATA_W;
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localparam RX_USER_W = s_axis_mac_rx.USER_W;
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localparam DATA_W = m_axis_pkt.DATA_W;
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localparam META_DATA_W = m_axis_meta_hdr.DATA_W;
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taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) mac_rx_int();
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taxi_axis_if #(.DATA_W(32), .USER_EN(1), .USER_W(RX_USER_W)) rx_pkt_hdr();
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taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) rx_bcast_int[2]();
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taxi_axis_async_fifo_adapter #(
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.DEPTH((MAC_DATA_W > DATA_W ? MAC_DATA_W : DATA_W)/8*32),
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.RAM_PIPELINE(1),
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.OUTPUT_FIFO_EN(1'b0),
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.FRAME_FIFO(1'b0),
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.USER_BAD_FRAME_VALUE(1'b1),
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.USER_BAD_FRAME_MASK(1'b1),
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.DROP_OVERSIZE_FRAME(1'b0),
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.DROP_BAD_FRAME(1'b0),
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.DROP_WHEN_FULL(1'b0),
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.MARK_WHEN_FULL(1'b1),
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.PAUSE_EN(1'b0)
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)
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rx_fifo_inst (
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/*
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* AXI4-Stream input (sink)
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*/
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.s_clk(mac_rx_clk),
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.s_rst(mac_rx_rst),
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.s_axis(s_axis_mac_rx),
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/*
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* AXI4-Stream output (source)
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*/
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.m_clk(clk),
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.m_rst(rst),
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.m_axis(mac_rx_int),
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/*
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* Pause
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*/
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.s_pause_req(1'b0),
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.s_pause_ack(),
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.m_pause_req(1'b0),
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.m_pause_ack(),
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/*
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* Status
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*/
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.s_status_depth(),
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.s_status_depth_commit(),
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.s_status_overflow(),
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.s_status_bad_frame(),
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.s_status_good_frame(),
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.m_status_depth(),
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.m_status_depth_commit(),
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.m_status_overflow(),
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.m_status_bad_frame(),
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.m_status_good_frame()
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);
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taxi_axis_broadcast #(
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.M_COUNT($size(rx_bcast_int))
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)
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rx_broadcast_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI4-Stream input (sink)
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*/
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.s_axis(mac_rx_int),
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/*
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* AXI4-Stream outputs (sources)
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*/
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.m_axis(rx_bcast_int)
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);
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zircon_ip_len_cksum #(
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.START_OFFSET(14)
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)
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rx_len_cksum_inst (
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.clk(clk),
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.rst(rst),
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/*
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* Packet passthrough
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*/
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.s_axis_pkt(rx_bcast_int[0]),
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.m_axis_pkt(m_axis_pkt),
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/*
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* Packet metadata output
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*/
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.m_axis_meta(m_axis_meta_len)
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);
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taxi_axis_adapter
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hdr_adapter_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI4-Stream input (sink)
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*/
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.s_axis(rx_bcast_int[1]),
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/*
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* AXI4-Stream output (source)
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*/
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.m_axis(rx_pkt_hdr)
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);
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zircon_ip_rx_parse #(
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.IPV6_EN(IPV6_EN),
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.HASH_EN(HASH_EN)
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)
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rx_parse_inst (
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.clk(clk),
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.rst(rst),
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/*
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* Packet header input
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*/
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.s_axis_pkt(rx_pkt_hdr),
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/*
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* Packet metadata output
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*/
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.m_axis_meta(m_axis_meta_hdr)
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);
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endmodule
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`resetall
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