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255b26d2f2dfa1438aa75c3a830617fffb4e0490
taxi-bsl/rtl/eth
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Alex Forencich 255b26d2f2 eth: Add GMII Ethernet MAC with FIFOs module and testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-02-16 22:17:22 -08:00
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taxi_axis_baser_rx_64.sv
eth: Add AXI stream 64-bit BASE-R Ethernet frame receiver module and testbench
2025-02-07 16:27:27 -08:00
taxi_axis_baser_tx_64.sv
eth: Invert TX completion output control
2025-02-07 23:24:28 -08:00
taxi_axis_gmii_rx.sv
eth: Add AXI stream GMII Ethernet frame receiver module and testbench
2025-02-07 16:12:58 -08:00
taxi_axis_gmii_tx.sv
eth: Invert TX completion output control
2025-02-07 23:24:28 -08:00
taxi_axis_xgmii_rx_32.sv
eth: Add AXI stream 32-bit XGMII Ethernet frame receiver module and testbench
2025-02-07 16:25:06 -08:00
taxi_axis_xgmii_rx_64.sv
eth: Add AXI stream 64-bit XGMII Ethernet frame receiver module and testbench
2025-02-07 16:25:54 -08:00
taxi_axis_xgmii_tx_32.sv
eth: Invert TX completion output control
2025-02-07 23:24:28 -08:00
taxi_axis_xgmii_tx_64.sv
eth: Invert TX completion output control
2025-02-07 23:24:28 -08:00
taxi_eth_mac_1g_fifo.f
eth: Add 1G Ethernet MAC module with FIFOs and testbench
2025-02-11 22:12:57 -08:00
taxi_eth_mac_1g_fifo.sv
eth: Add 1G Ethernet MAC module with FIFOs and testbench
2025-02-11 22:12:57 -08:00
taxi_eth_mac_1g_gmii_fifo.f
eth: Add GMII Ethernet MAC with FIFOs module and testbench
2025-02-16 22:17:22 -08:00
taxi_eth_mac_1g_gmii_fifo.sv
eth: Add GMII Ethernet MAC with FIFOs module and testbench
2025-02-16 22:17:22 -08:00
taxi_eth_mac_1g_gmii.f
eth: Add GMII Ethernet MAC module and testbench
2025-02-16 21:37:12 -08:00
taxi_eth_mac_1g_gmii.sv
eth: Add GMII Ethernet MAC module and testbench
2025-02-16 21:37:12 -08:00
taxi_eth_mac_1g_rgmii.f
eth: Add RGMII Ethernet MAC module and testbench
2025-02-16 22:05:59 -08:00
taxi_eth_mac_1g_rgmii.sv
eth: Add RGMII Ethernet MAC module and testbench
2025-02-16 22:05:59 -08:00
taxi_eth_mac_1g.f
eth: Add taxi_axis_if to MAC file list files
2025-02-11 15:54:15 -08:00
taxi_eth_mac_1g.sv
eth: Remove unnecessary PTP_TS_FMT_TOD parameter in 1G MAC module
2025-02-16 18:06:41 -08:00
taxi_eth_mac_10g_fifo.f
eth: Add 10G Ethernet MAC module with FIFOs and testbench
2025-02-13 13:47:54 -08:00
taxi_eth_mac_10g_fifo.sv
eth: Add 10G Ethernet MAC module with FIFOs and testbench
2025-02-13 13:47:54 -08:00
taxi_eth_mac_10g.f
eth: Add taxi_axis_if to MAC file list files
2025-02-11 15:54:15 -08:00
taxi_eth_mac_10g.sv
eth: Add 10G Ethernet MAC module and testbench
2025-02-08 21:26:03 -08:00
taxi_eth_mac_mii_fifo.f
eth: Add MII Ethernet MAC with FIFOs module and testbench
2025-02-16 22:16:54 -08:00
taxi_eth_mac_mii_fifo.sv
eth: Add MII Ethernet MAC with FIFOs module and testbench
2025-02-16 22:16:54 -08:00
taxi_eth_mac_mii.f
eth: Add MII Ethernet MAC module and testbench
2025-02-16 20:46:31 -08:00
taxi_eth_mac_mii.sv
eth: Add MII Ethernet MAC module and testbench
2025-02-16 20:46:31 -08:00
taxi_eth_mac_phy_10g_fifo.f
eth: Add 10G Ethernet MAC+PHY module with FIFOs and testbench
2025-02-13 13:48:54 -08:00
taxi_eth_mac_phy_10g_fifo.sv
eth: Add 10G Ethernet MAC+PHY module with FIFOs and testbench
2025-02-13 13:48:54 -08:00
taxi_eth_mac_phy_10g_rx.f
eth: Add taxi_axis_if to MAC file list files
2025-02-11 15:54:15 -08:00
taxi_eth_mac_phy_10g_rx.sv
eth: Add 10G Ethernet combined MAC+PHY module and testbench
2025-02-08 21:40:50 -08:00
taxi_eth_mac_phy_10g_tx.f
eth: Add taxi_axis_if to MAC file list files
2025-02-11 15:54:15 -08:00
taxi_eth_mac_phy_10g_tx.sv
eth: Add 10G Ethernet combined MAC+PHY module and testbench
2025-02-08 21:40:50 -08:00
taxi_eth_mac_phy_10g.f
eth: Add 10G Ethernet combined MAC+PHY module and testbench
2025-02-08 21:40:50 -08:00
taxi_eth_mac_phy_10g.sv
eth: Add 10G Ethernet combined MAC+PHY module and testbench
2025-02-08 21:40:50 -08:00
taxi_eth_phy_10g_rx_ber_mon.sv
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g_rx_frame_sync.sv
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g_rx_if.f
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g_rx_if.sv
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g_rx_watchdog.sv
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g_rx.f
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g_rx.sv
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g_tx_if.f
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g_tx_if.sv
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g_tx.f
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g_tx.sv
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g.f
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_eth_phy_10g.sv
eth: Add 10G PHY module and testbench
2025-02-04 17:10:21 -08:00
taxi_gmii_phy_if.f
eth: Add GMII PHY interface module
2025-02-16 21:34:49 -08:00
taxi_gmii_phy_if.sv
eth: Add GMII PHY interface module
2025-02-16 21:34:49 -08:00
taxi_mac_ctrl_rx.sv
eth: Add MAC control modules
2025-02-08 19:59:11 -08:00
taxi_mac_ctrl_tx.sv
eth: Add MAC control modules
2025-02-08 19:59:11 -08:00
taxi_mac_pause_ctrl_rx.sv
eth: Add MAC pause control modules
2025-02-05 21:11:14 -08:00
taxi_mac_pause_ctrl_tx.sv
eth: Add MAC pause control modules
2025-02-05 21:11:14 -08:00
taxi_mii_phy_if.f
eth: Add MII PHY interface module
2025-02-16 20:05:41 -08:00
taxi_mii_phy_if.sv
eth: Add MII PHY interface module
2025-02-16 20:05:41 -08:00
taxi_rgmii_phy_if.f
eth: Add RGMII PHY interface module
2025-02-16 21:50:42 -08:00
taxi_rgmii_phy_if.sv
eth: Add RGMII PHY interface module
2025-02-16 21:50:42 -08:00
taxi_xgmii_baser_dec_64.sv
eth: Add XGMII/BASE-R encode/decode modules and testbenches
2025-02-04 16:14:32 -08:00
taxi_xgmii_baser_enc_64.sv
eth: Add XGMII/BASE-R encode/decode modules and testbenches
2025-02-04 16:14:32 -08:00