84 lines
1.5 KiB
Systemverilog
84 lines
1.5 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* GT QPLL reset controller for UltraScale/UltraScale+ GTH/GTY
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*/
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module taxi_gt_qpll_reset #
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(
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parameter logic QPLL_PD = 1'b0,
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parameter CNT_W = 8
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* GT
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*/
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output wire logic gt_qpll_reset_out,
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output wire logic gt_qpll_pd_out,
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input wire logic gt_qpll_lock_in,
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/*
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* Control/status
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*/
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input wire logic qpll_reset_in = 1'b0,
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input wire logic qpll_pd_in = QPLL_PD,
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output wire logic qpll_lock_out
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);
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logic qpll_reset_reg = 1'b1;
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logic qpll_pd_reg = QPLL_PD;
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logic [CNT_W-1:0] qpll_reset_cnt_reg = '0;
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assign gt_qpll_reset_out = qpll_reset_reg;
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assign gt_qpll_pd_out = qpll_pd_reg;
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always_ff @(posedge clk) begin
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qpll_pd_reg <= qpll_pd_in;
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if (&qpll_reset_cnt_reg) begin
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qpll_reset_reg <= 1'b0;
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end else begin
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qpll_reset_cnt_reg <= qpll_reset_cnt_reg + 1;
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qpll_reset_reg <= 1'b1;
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end
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if (qpll_reset_in || qpll_pd_reg) begin
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qpll_reset_cnt_reg <= 0;
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end
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if (rst) begin
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qpll_reset_reg <= 1'b1;
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qpll_pd_reg <= QPLL_PD;
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qpll_reset_cnt_reg <= '0;
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end
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end
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taxi_sync_signal #(
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.WIDTH(1),
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.N(2)
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)
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qpll_lock_sync_inst (
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.clk(clk),
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.in(gt_qpll_lock_in),
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.out(qpll_lock_out)
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);
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endmodule
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`resetall
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