216 lines
14 KiB
Tcl
216 lines
14 KiB
Tcl
# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2014-2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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# XDC constraints for the Xilinx VC709
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# part: xc7vx690tffg1761-2
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# General configuration
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set_property CFGBVS GND [current_design]
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set_property CONFIG_VOLTAGE 1.8 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
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# 200 MHz system clock (U51)
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set_property -dict {LOC H19 IOSTANDARD DIFF_SSTL15_DCI} [get_ports clk_200mhz_p]
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set_property -dict {LOC G18 IOSTANDARD DIFF_SSTL15_DCI} [get_ports clk_200mhz_n]
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create_clock -period 5.0 -name clk_200mhz [get_ports clk_200mhz_p]
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# User clock (U34)
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#set_property -dict {LOC AL34 IOSTANDARD LVDS} [get_ports clk_user_p]
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#set_property -dict {LOC AK34 IOSTANDARD LVDS} [get_ports clk_user_n]
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#create_clock -period 6.4 -name clk_user [get_ports clk_user_p]
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# User SMA clock (J31/J32)
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#set_property -dict {LOC AJ32 IOSTANDARD LVDS} [get_ports clk_sma_p]
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#set_property -dict {LOC AK32 IOSTANDARD LVDS} [get_ports clk_sma_n]
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#create_clock -period 6.4 -name clk_sma [get_ports clk_sma_p]
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# 233.33 MHz DDR3 MIG clock (U13)
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#set_property -dict {LOC AY17 IOSTANDARD DIFF_SSTL15_DCI} [get_ports clk_233mhz_p]
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#set_property -dict {LOC AY18 IOSTANDARD DIFF_SSTL15_DCI} [get_ports clk_233mhz_n]
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#create_clock -period 4.285 -name clk_233mhz [get_ports clk_233mhz_p]
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# EMC clock (U40)
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#set_property -dict {LOC AP37 IOSTANDARD LVCMOS18} [get_ports emcclk]
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#create_clock -period 1.25 -name emcclk [get_ports emcclk]
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# LEDs
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set_property -dict {LOC AM39 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[0]}] ;# DS2
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set_property -dict {LOC AN39 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[1]}] ;# DS3
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set_property -dict {LOC AR37 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[2]}] ;# DS4
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set_property -dict {LOC AT37 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[3]}] ;# DS5
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set_property -dict {LOC AR35 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[4]}] ;# DS6
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set_property -dict {LOC AP41 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[5]}] ;# DS7
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set_property -dict {LOC AP42 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[6]}] ;# DS8
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set_property -dict {LOC AU39 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led[7]}] ;# DS9
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set_false_path -to [get_ports {led[*]}]
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set_output_delay 0 [get_ports {led[*]}]
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# Reset button
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set_property -dict {LOC AV40 IOSTANDARD LVCMOS18} [get_ports reset] ;# from SW8
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set_false_path -from [get_ports {reset}]
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set_input_delay 0 [get_ports {reset}]
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# Push buttons
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set_property -dict {LOC AR40 IOSTANDARD LVCMOS18} [get_ports btnu] ;# from SW3
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set_property -dict {LOC AW40 IOSTANDARD LVCMOS18} [get_ports btnl] ;# from SW7
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set_property -dict {LOC AP40 IOSTANDARD LVCMOS18} [get_ports btnd] ;# from SW5
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set_property -dict {LOC AU38 IOSTANDARD LVCMOS18} [get_ports btnr] ;# from SW4
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set_property -dict {LOC AV39 IOSTANDARD LVCMOS18} [get_ports btnc] ;# from SW6
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set_false_path -from [get_ports {btnu btnl btnd btnr btnc}]
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set_input_delay 0 [get_ports {btnu btnl btnd btnr btnc}]
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# DIP switches
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set_property -dict {LOC AV30 IOSTANDARD LVCMOS18} [get_ports {sw[0]}] ;# from SW2.1
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set_property -dict {LOC AY33 IOSTANDARD LVCMOS18} [get_ports {sw[1]}] ;# from SW2.2
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set_property -dict {LOC BA31 IOSTANDARD LVCMOS18} [get_ports {sw[2]}] ;# from SW2.3
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set_property -dict {LOC BA32 IOSTANDARD LVCMOS18} [get_ports {sw[3]}] ;# from SW2.4
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set_property -dict {LOC AW30 IOSTANDARD LVCMOS18} [get_ports {sw[4]}] ;# from SW2.5
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set_property -dict {LOC AY30 IOSTANDARD LVCMOS18} [get_ports {sw[5]}] ;# from SW2.6
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set_property -dict {LOC BA30 IOSTANDARD LVCMOS18} [get_ports {sw[6]}] ;# from SW2.7
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set_property -dict {LOC BB31 IOSTANDARD LVCMOS18} [get_ports {sw[7]}] ;# from SW2.8
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set_false_path -from [get_ports {sw[*]}]
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set_input_delay 0 [get_ports {sw[*]}]
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# UART (U44 CP2103)
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set_property -dict {LOC AU36 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# U44.24 RXD_I
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set_property -dict {LOC AU33 IOSTANDARD LVCMOS18} [get_ports {uart_rxd}] ;# U44.25 TXD_O
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set_property -dict {LOC AT32 IOSTANDARD LVCMOS18} [get_ports {uart_rts}] ;# U44.23 RTS_O_B
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set_property -dict {LOC AR34 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# U44.22 CTS_I_B
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set_false_path -to [get_ports {uart_txd uart_cts}]
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set_output_delay 0 [get_ports {uart_txd uart_cts}]
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set_false_path -from [get_ports {uart_rxd uart_rts}]
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set_input_delay 0 [get_ports {uart_rxd uart_rts}]
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# I2C interface
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set_property -dict {LOC AT35 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_scl]
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set_property -dict {LOC AU32 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_sda]
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set_property -dict {LOC AY42 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_mux_reset]
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set_false_path -to [get_ports {i2c_sda i2c_scl i2c_mux_reset}]
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set_output_delay 0 [get_ports {i2c_sda i2c_scl i2c_mux_reset}]
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set_false_path -from [get_ports {i2c_sda i2c_scl}]
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set_input_delay 0 [get_ports {i2c_sda i2c_scl}]
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# SFP+ Interfaces
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# NOTE: modules 0 and 1 swapped relative to schematic net names to match board layout
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set_property -dict {LOC AN2 } [get_ports {sfp_tx_p[0]}] ;# MGTHTXP2_113 GTHE2_CHANNEL_X1Y13 / GTHE2_COMMON_X1Y3
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set_property -dict {LOC AN1 } [get_ports {sfp_tx_n[0]}] ;# MGTHTXN2_113 GTHE2_CHANNEL_X1Y13 / GTHE2_COMMON_X1Y3
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set_property -dict {LOC AM8 } [get_ports {sfp_rx_p[0]}] ;# MGTHRXP2_113 GTHE2_CHANNEL_X1Y13 / GTHE2_COMMON_X1Y3
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set_property -dict {LOC AM7 } [get_ports {sfp_rx_n[0]}] ;# MGTHRXN2_113 GTHE2_CHANNEL_X1Y13 / GTHE2_COMMON_X1Y3
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set_property -dict {LOC AP4 } [get_ports {sfp_tx_p[1]}] ;# MGTHTXP3_113 GTHE2_CHANNEL_X1Y12 / GTHE2_COMMON_X1Y3
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set_property -dict {LOC AP3 } [get_ports {sfp_tx_n[1]}] ;# MGTHTXN3_113 GTHE2_CHANNEL_X1Y12 / GTHE2_COMMON_X1Y3
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set_property -dict {LOC AN6 } [get_ports {sfp_rx_p[1]}] ;# MGTHRXP3_113 GTHE2_CHANNEL_X1Y12 / GTHE2_COMMON_X1Y3
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set_property -dict {LOC AN5 } [get_ports {sfp_rx_n[1]}] ;# MGTHRXN3_113 GTHE2_CHANNEL_X1Y12 / GTHE2_COMMON_X1Y3
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set_property -dict {LOC AM4 } [get_ports {sfp_tx_p[2]}] ;# MGTHTXP1_113 GTHE2_CHANNEL_X1Y14 / GTHE2_COMMON_X1Y3
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set_property -dict {LOC AM3 } [get_ports {sfp_tx_n[2]}] ;# MGTHTXN1_113 GTHE2_CHANNEL_X1Y14 / GTHE2_COMMON_X1Y3
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set_property -dict {LOC AL6 } [get_ports {sfp_rx_p[2]}] ;# MGTHRXP1_113 GTHE2_CHANNEL_X1Y14 / GTHE2_COMMON_X1Y3
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set_property -dict {LOC AL5 } [get_ports {sfp_rx_n[2]}] ;# MGTHRXN1_113 GTHE2_CHANNEL_X1Y14 / GTHE2_COMMON_X1Y3
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set_property -dict {LOC AL2 } [get_ports {sfp_tx_p[3]}] ;# MGTHTXP0_113 GTHE2_CHANNEL_X1Y15 / GTHE2_COMMON_X1Y3
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set_property -dict {LOC AL1 } [get_ports {sfp_tx_n[3]}] ;# MGTHTXN0_113 GTHE2_CHANNEL_X1Y15 / GTHE2_COMMON_X1Y3
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set_property -dict {LOC AJ6 } [get_ports {sfp_rx_p[3]}] ;# MGTHRXP0_113 GTHE2_CHANNEL_X1Y15 / GTHE2_COMMON_X1Y3
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set_property -dict {LOC AJ5 } [get_ports {sfp_rx_n[3]}] ;# MGTHRXN0_113 GTHE2_CHANNEL_X1Y15 / GTHE2_COMMON_X1Y3
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set_property -dict {LOC AH8 } [get_ports sfp_mgt_refclk_p] ;# MGTREFCLK0P_113 from U24.28
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set_property -dict {LOC AH7 } [get_ports sfp_mgt_refclk_n] ;# MGTREFCLK0N_113 from U24.29
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# set_property -dict {LOC AK8 } [get_ports sma_mgt_refclk_p] ;# MGTREFCLK1P_113 from J25
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# set_property -dict {LOC AK7 } [get_ports sma_mgt_refclk_n] ;# MGTREFCLK1N_113 from J26
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#set_property -dict {LOC AW32 IOSTANDARD LVDS} [get_ports sfp_recclk_p] ;# to IC20.16
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#set_property -dict {LOC AW33 IOSTANDARD LVDS} [get_ports sfp_recclk_n] ;# to IC20.17
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set_property -dict {LOC AT36 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports si5324_rst]
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set_property -dict {LOC AU34 IOSTANDARD LVCMOS18 PULLUP true} [get_ports si5324_int]
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set_property -dict {LOC AA42 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_mod_detect[0]}]
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set_property -dict {LOC AB42 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_mod_detect[1]}]
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set_property -dict {LOC AC39 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_mod_detect[2]}]
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set_property -dict {LOC AC41 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_mod_detect[3]}]
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set_property -dict {LOC AB38 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[0][0]}]
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set_property -dict {LOC AB39 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[0][1]}]
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set_property -dict {LOC W40 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[1][0]}]
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set_property -dict {LOC Y40 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[1][1]}]
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set_property -dict {LOC AD42 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[2][0]}]
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set_property -dict {LOC AE42 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[2][1]}]
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set_property -dict {LOC AE39 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[3][0]}]
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set_property -dict {LOC AE40 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_rs[3][1]}]
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set_property -dict {LOC AA40 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_los[0]}]
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set_property -dict {LOC Y39 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_los[1]}]
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set_property -dict {LOC AD38 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_los[2]}]
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set_property -dict {LOC AD40 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_los[3]}]
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set_property -dict {LOC Y42 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[0]}]
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set_property -dict {LOC AB41 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[1]}]
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set_property -dict {LOC AC38 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[2]}]
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set_property -dict {LOC AC40 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_tx_disable[3]}]
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set_property -dict {LOC AA39 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_tx_fault[0]}]
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set_property -dict {LOC Y38 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_tx_fault[1]}]
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set_property -dict {LOC AA41 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_tx_fault[2]}]
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set_property -dict {LOC AE38 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {sfp_tx_fault[3]}]
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# 156.25 MHz MGT reference clock
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create_clock -period 6.4 -name sfp_mgt_refclk [get_ports sfp_mgt_refclk_p]
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# 156.25 MHz MGT reference clock
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#create_clock -period 6.4 -name sma_mgt_refclk [get_ports sma_mgt_refclk_p]
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set_false_path -to [get_ports {si5324_rst}]
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set_output_delay 0 [get_ports {si5324_rst}]
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set_false_path -from [get_ports {si5324_int}]
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set_input_delay 0 [get_ports {si5324_int}]
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set_false_path -from [get_ports {sfp_mod_detect[*] sfp_los[*] sfp_tx_fault[*]}]
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set_input_delay 0 [get_ports {sfp_mod_detect[*] sfp_los[*] sfp_tx_fault[*]}]
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set_false_path -to [get_ports {sfp_rs[*][*] sfp_tx_disable[*]}]
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set_output_delay 0 [get_ports {sfp_rs[*][*] sfp_tx_disable[*]}]
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# PCIe Interface
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#set_property -dict {LOC Y4 } [get_ports {pcie_rx_p[0]}] ;# MGTHTXP3_115 GTHE2_CHANNEL_X1Y23 / GTHE2_COMMON_X1Y5
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#set_property -dict {LOC Y3 } [get_ports {pcie_rx_n[0]}] ;# MGTHTXN3_115 GTHE2_CHANNEL_X1Y23 / GTHE2_COMMON_X1Y5
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#set_property -dict {LOC W2 } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_115 GTHE2_CHANNEL_X1Y23 / GTHE2_COMMON_X1Y5
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#set_property -dict {LOC W1 } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_115 GTHE2_CHANNEL_X1Y23 / GTHE2_COMMON_X1Y5
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#set_property -dict {LOC AA6 } [get_ports {pcie_rx_p[1]}] ;# MGTHTXP2_115 GTHE2_CHANNEL_X1Y22 / GTHE2_COMMON_X1Y5
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#set_property -dict {LOC AA5 } [get_ports {pcie_rx_n[1]}] ;# MGTHTXN2_115 GTHE2_CHANNEL_X1Y22 / GTHE2_COMMON_X1Y5
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#set_property -dict {LOC AA2 } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_115 GTHE2_CHANNEL_X1Y22 / GTHE2_COMMON_X1Y5
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#set_property -dict {LOC AA1 } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_115 GTHE2_CHANNEL_X1Y22 / GTHE2_COMMON_X1Y5
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#set_property -dict {LOC AB4 } [get_ports {pcie_rx_p[2]}] ;# MGTHTXP1_115 GTHE2_CHANNEL_X1Y21 / GTHE2_COMMON_X1Y5
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#set_property -dict {LOC AB3 } [get_ports {pcie_rx_n[2]}] ;# MGTHTXN1_115 GTHE2_CHANNEL_X1Y21 / GTHE2_COMMON_X1Y5
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#set_property -dict {LOC AC2 } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_115 GTHE2_CHANNEL_X1Y21 / GTHE2_COMMON_X1Y5
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#set_property -dict {LOC AC1 } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_115 GTHE2_CHANNEL_X1Y21 / GTHE2_COMMON_X1Y5
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#set_property -dict {LOC AC6 } [get_ports {pcie_rx_p[3]}] ;# MGTHTXP0_115 GTHE2_CHANNEL_X1Y20 / GTHE2_COMMON_X1Y5
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#set_property -dict {LOC AC5 } [get_ports {pcie_rx_n[3]}] ;# MGTHTXN0_115 GTHE2_CHANNEL_X1Y20 / GTHE2_COMMON_X1Y5
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#set_property -dict {LOC AE2 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_115 GTHE2_CHANNEL_X1Y20 / GTHE2_COMMON_X1Y5
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#set_property -dict {LOC AE1 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_115 GTHE2_CHANNEL_X1Y20 / GTHE2_COMMON_X1Y5
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#set_property -dict {LOC AD4 } [get_ports {pcie_rx_p[4]}] ;# MGTHTXP3_114 GTHE2_CHANNEL_X1Y19 / GTHE2_COMMON_X1Y4
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#set_property -dict {LOC AD3 } [get_ports {pcie_rx_n[4]}] ;# MGTHTXN3_114 GTHE2_CHANNEL_X1Y19 / GTHE2_COMMON_X1Y4
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#set_property -dict {LOC AG2 } [get_ports {pcie_tx_p[4]}] ;# MGTHTXP3_114 GTHE2_CHANNEL_X1Y19 / GTHE2_COMMON_X1Y4
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#set_property -dict {LOC AG1 } [get_ports {pcie_tx_n[4]}] ;# MGTHTXN3_114 GTHE2_CHANNEL_X1Y19 / GTHE2_COMMON_X1Y4
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#set_property -dict {LOC AE6 } [get_ports {pcie_rx_p[5]}] ;# MGTHTXP2_114 GTHE2_CHANNEL_X1Y18 / GTHE2_COMMON_X1Y4
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#set_property -dict {LOC AE5 } [get_ports {pcie_rx_n[5]}] ;# MGTHTXN2_114 GTHE2_CHANNEL_X1Y18 / GTHE2_COMMON_X1Y4
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#set_property -dict {LOC AH4 } [get_ports {pcie_tx_p[5]}] ;# MGTHTXP2_114 GTHE2_CHANNEL_X1Y18 / GTHE2_COMMON_X1Y4
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#set_property -dict {LOC AH3 } [get_ports {pcie_tx_n[5]}] ;# MGTHTXN2_114 GTHE2_CHANNEL_X1Y18 / GTHE2_COMMON_X1Y4
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#set_property -dict {LOC AF4 } [get_ports {pcie_rx_p[6]}] ;# MGTHTXP1_114 GTHE2_CHANNEL_X1Y17 / GTHE2_COMMON_X1Y4
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#set_property -dict {LOC AF3 } [get_ports {pcie_rx_n[6]}] ;# MGTHTXN1_114 GTHE2_CHANNEL_X1Y17 / GTHE2_COMMON_X1Y4
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#set_property -dict {LOC AJ2 } [get_ports {pcie_tx_p[6]}] ;# MGTHTXP1_114 GTHE2_CHANNEL_X1Y17 / GTHE2_COMMON_X1Y4
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#set_property -dict {LOC AJ1 } [get_ports {pcie_tx_n[6]}] ;# MGTHTXN1_114 GTHE2_CHANNEL_X1Y17 / GTHE2_COMMON_X1Y4
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#set_property -dict {LOC AG6 } [get_ports {pcie_rx_p[7]}] ;# MGTHTXP0_114 GTHE2_CHANNEL_X1Y16 / GTHE2_COMMON_X1Y4
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#set_property -dict {LOC AG5 } [get_ports {pcie_rx_n[7]}] ;# MGTHTXN0_114 GTHE2_CHANNEL_X1Y16 / GTHE2_COMMON_X1Y4
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#set_property -dict {LOC AK4 } [get_ports {pcie_tx_p[7]}] ;# MGTHTXP0_114 GTHE2_CHANNEL_X1Y16 / GTHE2_COMMON_X1Y4
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#set_property -dict {LOC AK3 } [get_ports {pcie_tx_n[7]}] ;# MGTHTXN0_114 GTHE2_CHANNEL_X1Y16 / GTHE2_COMMON_X1Y4
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#set_property -dict {LOC AB8 } [get_ports pcie_mgt_refclk_p] ;# MGTREFCLK1P_115
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#set_property -dict {LOC AB7 } [get_ports pcie_mgt_refclk_n] ;# MGTREFCLK1N_115
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#set_property -dict {LOC AV35 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]
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# 100 MHz MGT reference clock
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#create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p]
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#set_false_path -from [get_ports {pcie_reset_n}]
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#set_input_delay 0 [get_ports {pcie_reset_n}]
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