Alex Forencich fc1e0efad7 ptp: Add PTP TD rel2tod timestamp reconstruction module and testbench ...

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2025-02-13 22:07:46 -08:00

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axis

axis: Fix parameter sizing in AXI stream FIFOs

2025-02-13 13:46:56 -08:00

eth

eth: Add 10G Ethernet MAC+PHY module with FIFOs and testbench

2025-02-13 13:48:54 -08:00

io

io: Add switch debounce module

2025-02-04 00:16:34 -08:00

lfsr

lfsr: Add LFSR descrambler module and testbench

2025-02-05 15:29:12 -08:00

lss

lss: Add UART module and testbench

2025-02-03 15:02:48 -08:00

ptp

ptp: Add PTP TD rel2tod timestamp reconstruction module and testbench

2025-02-13 22:07:46 -08:00

sync

sync: Add signal synchronizer module

2025-02-03 23:43:18 -08:00