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Alex Forencich c6cbb57fe7 lss: Extract UART data width setting from interface 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-02-26 14:15:42 -08:00
..
Makefile
lss: Add UART module and testbench
2025-02-03 15:02:48 -08:00
test_taxi_uart.py
lss: Add UART module and testbench
2025-02-03 15:02:48 -08:00
test_taxi_uart.sv
lss: Extract UART data width setting from interface
2025-02-26 14:15:42 -08:00