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6c9026bccf0b2694a1d628ca9c51d83079f164b5
taxi-bsl/src/eth/example
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Alex Forencich 6c9026bccf eth/example/HTG9200: Fix refclock frequency in testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-09-05 07:15:26 -07:00
..
ADM_PCIE_9V3/fpga
eth: Rename gearbox start signals to sync
2025-06-12 15:45:07 -07:00
Alveo/fpga
eth: Rename gearbox start signals to sync
2025-06-12 15:45:07 -07:00
Arty/fpga
Reorganize repository
2025-05-18 12:25:59 -07:00
fb2CG/fpga
eth: Rename gearbox start signals to sync
2025-06-12 15:45:07 -07:00
HTG940/fpga
Reorganize repository
2025-05-18 12:25:59 -07:00
HTG9200/fpga
eth/example/HTG9200: Fix refclock frequency in testbench
2025-09-05 07:15:26 -07:00
KC705/fpga
Reorganize repository
2025-05-18 12:25:59 -07:00
KCU105/fpga
eth: Update 10G-only example designs to use 32-bit MACs
2025-06-17 23:19:30 -07:00
KR260/fpga
eth: Update 10G-only example designs to use 32-bit MACs
2025-06-17 23:19:30 -07:00
Nexus_K3P_Q/fpga
eth: Rename gearbox start signals to sync
2025-06-12 15:45:07 -07:00
Nexus_K3P_S/fpga
eth: Rename gearbox start signals to sync
2025-06-12 15:45:07 -07:00
VCU108/fpga
eth: Rename gearbox start signals to sync
2025-06-12 15:45:07 -07:00
VCU118/fpga
eth: Rename gearbox start signals to sync
2025-06-12 15:45:07 -07:00
XUPP3R/fpga
eth: Rename gearbox start signals to sync
2025-06-12 15:45:07 -07:00
ZCU102/fpga
eth: Update 10G-only example designs to use 32-bit MACs
2025-06-17 23:19:30 -07:00
ZCU106/fpga
eth: Update 10G-only example designs to use 32-bit MACs
2025-06-17 23:19:30 -07:00
ZCU111/fpga
eth: Add RFDC to ZCU111 example design
2025-08-24 11:26:14 -07:00