608 lines
19 KiB
Systemverilog
608 lines
19 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2018-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 crossbar (write)
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*/
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module taxi_axi_crossbar_wr #
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(
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// Number of AXI inputs (slave interfaces)
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parameter S_COUNT = 4,
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// Number of AXI outputs (master interfaces)
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parameter M_COUNT = 4,
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// Address width in bits for address decoding
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parameter ADDR_W = 32,
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// TODO fix parametrization once verilator issue 5890 is fixed
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// Number of concurrent unique IDs for each slave interface
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// S_COUNT concatenated fields of 32 bits
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parameter S_THREADS = {S_COUNT{32'd2}},
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// Number of concurrent operations for each slave interface
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// S_COUNT concatenated fields of 32 bits
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parameter S_ACCEPT = {S_COUNT{32'd16}},
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// Number of regions per master interface
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parameter M_REGIONS = 1,
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// Master interface base addresses
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// M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_W bits
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// set to zero for default addressing based on M_ADDR_W
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parameter M_BASE_ADDR = '0,
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// Master interface address widths
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// M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
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parameter M_ADDR_W = {M_COUNT{{M_REGIONS{32'd24}}}},
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// Write connections between interfaces
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// M_COUNT concatenated fields of S_COUNT bits
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parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
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// Number of concurrent operations for each master interface
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// M_COUNT concatenated fields of 32 bits
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parameter M_ISSUE = {M_COUNT{32'd4}},
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// Secure master (fail operations based on awprot/arprot)
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// M_COUNT bits
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parameter M_SECURE = {M_COUNT{1'b0}},
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// Slave interface AW channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S_AW_REG_TYPE = {S_COUNT{2'd0}},
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// Slave interface W channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S_W_REG_TYPE = {S_COUNT{2'd0}},
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// Slave interface B channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S_B_REG_TYPE = {S_COUNT{2'd1}},
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// Master interface AW channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},
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// Master interface W channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M_W_REG_TYPE = {M_COUNT{2'd2}},
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// Master interface B channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M_B_REG_TYPE = {M_COUNT{2'd0}}
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI4 slave interfaces
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*/
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taxi_axi_if.wr_slv s_axi_wr[S_COUNT],
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/*
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* AXI4 master interfaces
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*/
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taxi_axi_if.wr_mst m_axi_wr[M_COUNT]
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);
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// extract parameters
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localparam DATA_W = s_axi_wr[0].DATA_W;
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localparam S_ADDR_W = s_axi_wr[0].ADDR_W;
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localparam STRB_W = s_axi_wr[0].STRB_W;
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localparam S_ID_W = s_axi_wr[0].ID_W;
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localparam M_ID_W = m_axi_wr[0].ID_W;
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localparam logic AWUSER_EN = s_axi_wr[0].AWUSER_EN && m_axi_wr[0].AWUSER_EN;
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localparam AWUSER_W = s_axi_wr[0].AWUSER_W;
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localparam logic WUSER_EN = s_axi_wr[0].WUSER_EN && m_axi_wr[0].WUSER_EN;
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localparam WUSER_W = s_axi_wr[0].WUSER_W;
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localparam logic BUSER_EN = s_axi_wr[0].BUSER_EN && m_axi_wr[0].BUSER_EN;
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localparam BUSER_W = s_axi_wr[0].BUSER_W;
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localparam AXI_M_ADDR_W = m_axi_wr[0].ADDR_W;
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localparam CL_S_COUNT = $clog2(S_COUNT);
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localparam CL_M_COUNT = $clog2(M_COUNT);
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localparam CL_S_COUNT_INT = CL_S_COUNT > 0 ? CL_S_COUNT : 1;
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localparam CL_M_COUNT_INT = CL_M_COUNT > 0 ? CL_M_COUNT : 1;
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localparam M_COUNT_P1 = M_COUNT+1;
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localparam CL_M_COUNT_P1 = $clog2(M_COUNT_P1);
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localparam [S_COUNT-1:0][31:0] S_THREADS_INT = S_THREADS;
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localparam [S_COUNT-1:0][31:0] S_ACCEPT_INT = S_ACCEPT;
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localparam [M_COUNT-1:0][31:0] M_ISSUE_INT = M_ISSUE;
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// check configuration
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if (s_axi_wr[0].ADDR_W != ADDR_W)
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$fatal(0, "Error: Interface ADDR_W parameter mismatch (instance %m)");
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if (m_axi_wr[0].DATA_W != DATA_W)
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$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
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if (m_axi_wr[0].STRB_W != STRB_W)
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$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
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if (M_ID_W < S_ID_W+$clog2(S_COUNT))
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$fatal(0, "Error: M_ID_W must be at least $clog2(S_COUNT) larger than S_ID_W (instance %m)");
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wire [S_ID_W-1:0] int_s_axi_awid[S_COUNT];
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wire [ADDR_W-1:0] int_s_axi_awaddr[S_COUNT];
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wire [7:0] int_s_axi_awlen[S_COUNT];
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wire [2:0] int_s_axi_awsize[S_COUNT];
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wire [1:0] int_s_axi_awburst[S_COUNT];
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wire int_s_axi_awlock[S_COUNT];
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wire [3:0] int_s_axi_awcache[S_COUNT];
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wire [2:0] int_s_axi_awprot[S_COUNT];
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wire [3:0] int_s_axi_awqos[S_COUNT];
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wire [3:0] int_s_axi_awregion[S_COUNT];
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wire [AWUSER_W-1:0] int_s_axi_awuser[S_COUNT];
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logic [M_COUNT-1:0] int_axi_awvalid[S_COUNT];
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logic [S_COUNT-1:0] int_axi_awready[M_COUNT];
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wire [DATA_W-1:0] int_s_axi_wdata[S_COUNT];
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wire [STRB_W-1:0] int_s_axi_wstrb[S_COUNT];
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wire int_s_axi_wlast[S_COUNT];
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wire [WUSER_W-1:0] int_s_axi_wuser[S_COUNT];
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logic [M_COUNT-1:0] int_axi_wvalid[S_COUNT];
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logic [S_COUNT-1:0] int_axi_wready[M_COUNT];
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wire [M_ID_W-1:0] int_m_axi_bid[M_COUNT];
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wire [1:0] int_m_axi_bresp[M_COUNT];
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wire [BUSER_W-1:0] int_m_axi_buser[M_COUNT];
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logic [S_COUNT-1:0] int_axi_bvalid[M_COUNT];
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logic [M_COUNT-1:0] int_axi_bready[S_COUNT];
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for (genvar m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces
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taxi_axi_if #(
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.DATA_W(s_axi_wr[0].DATA_W),
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.ADDR_W(s_axi_wr[0].ADDR_W),
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.STRB_W(s_axi_wr[0].STRB_W),
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.ID_W(s_axi_wr[0].ID_W),
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.AWUSER_EN(s_axi_wr[0].AWUSER_EN),
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.AWUSER_W(s_axi_wr[0].AWUSER_W),
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.WUSER_EN(s_axi_wr[0].WUSER_EN),
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.WUSER_W(s_axi_wr[0].WUSER_W),
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.BUSER_EN(s_axi_wr[0].BUSER_EN),
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.BUSER_W(s_axi_wr[0].BUSER_W)
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) int_axi();
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// S side register
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taxi_axi_register_wr #(
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.AW_REG_TYPE(S_AW_REG_TYPE[m*2 +: 2]),
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.W_REG_TYPE(S_W_REG_TYPE[m*2 +: 2]),
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.B_REG_TYPE(S_B_REG_TYPE[m*2 +: 2])
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)
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reg_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI4 slave interface
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*/
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.s_axi_wr(s_axi_wr[m]),
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/*
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* AXI4 master interface
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*/
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.m_axi_wr(int_axi)
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);
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// address decode and admission control
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wire [CL_M_COUNT_INT-1:0] a_select;
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wire m_axi_avalid;
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wire m_axi_aready;
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wire [CL_M_COUNT_INT-1:0] m_wc_select;
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wire m_wc_decerr;
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wire m_wc_valid;
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wire m_wc_ready;
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wire m_rc_decerr;
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wire m_rc_valid;
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wire m_rc_ready;
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wire [S_ID_W-1:0] s_cpl_id;
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wire s_cpl_valid;
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taxi_axi_crossbar_addr #(
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.S(m),
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.S_COUNT(S_COUNT),
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.M_COUNT(M_COUNT),
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.SEL_W(CL_M_COUNT_INT),
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.ADDR_W(ADDR_W),
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.ID_W(S_ID_W),
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.S_THREADS(S_THREADS_INT[m]),
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.S_ACCEPT(S_ACCEPT_INT[m]),
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.M_REGIONS(M_REGIONS),
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.M_BASE_ADDR(M_BASE_ADDR),
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.M_ADDR_W(M_ADDR_W),
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.M_CONNECT(M_CONNECT),
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.M_SECURE(M_SECURE),
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.WC_OUTPUT(1)
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)
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addr_inst (
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.clk(clk),
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.rst(rst),
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/*
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* Address input
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*/
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.s_axi_aid(int_axi.awid),
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.s_axi_aaddr(int_axi.awaddr),
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.s_axi_aprot(int_axi.awprot),
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.s_axi_aqos(int_axi.awqos),
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.s_axi_avalid(int_axi.awvalid),
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.s_axi_aready(int_axi.awready),
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/*
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* Address output
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*/
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.m_axi_aregion(int_s_axi_awregion[m]),
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.m_select(a_select),
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.m_axi_avalid(m_axi_avalid),
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.m_axi_aready(m_axi_aready),
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/*
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* Write command output
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*/
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.m_wc_select(m_wc_select),
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.m_wc_decerr(m_wc_decerr),
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.m_wc_valid(m_wc_valid),
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.m_wc_ready(m_wc_ready),
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/*
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* Response command output
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*/
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.m_rc_decerr(m_rc_decerr),
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.m_rc_valid(m_rc_valid),
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.m_rc_ready(m_rc_ready),
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/*
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* Completion input
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*/
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.s_cpl_id(s_cpl_id),
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.s_cpl_valid(s_cpl_valid)
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);
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assign int_s_axi_awid[m] = int_axi.awid;
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assign int_s_axi_awaddr[m] = int_axi.awaddr;
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assign int_s_axi_awlen[m] = int_axi.awlen;
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assign int_s_axi_awsize[m] = int_axi.awsize;
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assign int_s_axi_awburst[m] = int_axi.awburst;
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assign int_s_axi_awlock[m] = int_axi.awlock;
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assign int_s_axi_awcache[m] = int_axi.awcache;
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assign int_s_axi_awprot[m] = int_axi.awprot;
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assign int_s_axi_awqos[m] = int_axi.awqos;
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assign int_s_axi_awuser[m] = int_axi.awuser;
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always_comb begin
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int_axi_awvalid[m] = '0;
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int_axi_awvalid[m][a_select] = m_axi_avalid;
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end
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assign m_axi_aready = int_axi_awready[a_select][m];
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// write command handling
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logic [CL_M_COUNT_INT-1:0] w_select_reg = '0, w_select_next;
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logic w_drop_reg = 1'b0, w_drop_next;
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logic w_select_valid_reg = 1'b0, w_select_valid_next;
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assign m_wc_ready = !w_select_valid_reg;
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always_comb begin
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w_select_next = w_select_reg;
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w_drop_next = w_drop_reg && !(int_axi.wvalid && int_axi.wready && int_axi.wlast);
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w_select_valid_next = w_select_valid_reg && !(int_axi.wvalid && int_axi.wready && int_axi.wlast);
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if (m_wc_valid && !w_select_valid_reg) begin
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w_select_next = m_wc_select;
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w_drop_next = m_wc_decerr;
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w_select_valid_next = m_wc_valid;
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end
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end
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always_ff @(posedge clk) begin
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w_select_valid_reg <= w_select_valid_next;
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w_select_reg <= w_select_next;
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w_drop_reg <= w_drop_next;
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if (rst) begin
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w_select_valid_reg <= 1'b0;
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end
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end
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// write data forwarding
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assign int_s_axi_wdata[m] = int_axi.wdata;
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assign int_s_axi_wstrb[m] = int_axi.wstrb;
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assign int_s_axi_wlast[m] = int_axi.wlast;
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assign int_s_axi_wuser[m] = int_axi.wuser;
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always_comb begin
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int_axi_wvalid[m] = '0;
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int_axi_wvalid[m][w_select_reg] = int_axi.wvalid && w_select_valid_reg && !w_drop_reg;
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end
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assign int_axi.wready = int_axi_wready[w_select_reg][m] || w_drop_reg;
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// decode error handling
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logic [S_ID_W-1:0] decerr_m_axi_bid_reg = '0, decerr_m_axi_bid_next;
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logic decerr_m_axi_bvalid_reg = 1'b0, decerr_m_axi_bvalid_next;
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wire decerr_m_axi_bready;
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assign m_rc_ready = !decerr_m_axi_bvalid_reg;
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always_comb begin
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decerr_m_axi_bid_next = decerr_m_axi_bid_reg;
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decerr_m_axi_bvalid_next = decerr_m_axi_bvalid_reg;
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if (decerr_m_axi_bvalid_reg) begin
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if (decerr_m_axi_bready) begin
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decerr_m_axi_bvalid_next = 1'b0;
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end
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end else if (m_rc_valid && m_rc_ready) begin
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decerr_m_axi_bid_next = int_s_axi_awid[m];
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decerr_m_axi_bvalid_next = 1'b1;
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end
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end
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always_ff @(posedge clk) begin
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if (rst) begin
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decerr_m_axi_bvalid_reg <= 1'b0;
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end else begin
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decerr_m_axi_bvalid_reg <= decerr_m_axi_bvalid_next;
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end
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decerr_m_axi_bid_reg <= decerr_m_axi_bid_next;
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end
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// write response arbitration
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wire [M_COUNT_P1-1:0] b_req;
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wire [M_COUNT_P1-1:0] b_ack;
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wire [M_COUNT_P1-1:0] b_grant;
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wire b_grant_valid;
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wire [CL_M_COUNT_P1-1:0] b_grant_index;
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taxi_arbiter #(
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.PORTS(M_COUNT_P1),
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.ARB_ROUND_ROBIN(1),
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.ARB_BLOCK(1),
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.ARB_BLOCK_ACK(1),
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.LSB_HIGH_PRIO(1)
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)
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b_arb_inst (
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.clk(clk),
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.rst(rst),
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.req(b_req),
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.ack(b_ack),
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.grant(b_grant),
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.grant_valid(b_grant_valid),
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.grant_index(b_grant_index)
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);
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// write response mux
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always_comb begin
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if (b_grant_index == CL_M_COUNT_P1'(M_COUNT_P1-1)) begin
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int_axi.bid = decerr_m_axi_bid_reg;
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int_axi.bresp = 2'b11;
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int_axi.buser = '0;
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int_axi.bvalid = decerr_m_axi_bvalid_reg & b_grant_valid;
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end else begin
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int_axi.bid = S_ID_W'(int_m_axi_bid[b_grant_index[CL_M_COUNT_INT-1:0]]);
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int_axi.bresp = int_m_axi_bresp[b_grant_index[CL_M_COUNT_INT-1:0]];
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int_axi.buser = int_m_axi_buser[b_grant_index[CL_M_COUNT_INT-1:0]];
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int_axi.bvalid = int_axi_bvalid[b_grant_index[CL_M_COUNT_INT-1:0]][m] & b_grant_valid;
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end
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end
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always_comb begin
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int_axi_bready[m] = '0;
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int_axi_bready[m][b_grant_index[CL_M_COUNT_INT-1:0]] = b_grant_valid && int_axi.bready;
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end
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assign decerr_m_axi_bready = (b_grant_valid && int_axi.bready) && (b_grant_index == CL_M_COUNT_P1'(M_COUNT_P1-1));
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for (genvar n = 0; n < M_COUNT; n = n + 1) begin
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assign b_req[n] = int_axi_bvalid[n][m] && !b_grant[n];
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assign b_ack[n] = b_grant[n] && int_axi_bvalid[n][m] && int_axi.bready;
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end
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assign b_req[M_COUNT_P1-1] = decerr_m_axi_bvalid_reg && !b_grant[M_COUNT_P1-1];
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assign b_ack[M_COUNT_P1-1] = b_grant[M_COUNT_P1-1] && decerr_m_axi_bvalid_reg && int_axi.bready;
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assign s_cpl_id = int_axi.bid;
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assign s_cpl_valid = int_axi.bvalid && int_axi.bready;
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end // s_ifaces
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for (genvar n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces
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|
|
|
taxi_axi_if #(
|
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.DATA_W(m_axi_wr[0].DATA_W),
|
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.ADDR_W(m_axi_wr[0].ADDR_W),
|
|
.STRB_W(m_axi_wr[0].STRB_W),
|
|
.ID_W(m_axi_wr[0].ID_W),
|
|
.AWUSER_EN(m_axi_wr[0].AWUSER_EN),
|
|
.AWUSER_W(m_axi_wr[0].AWUSER_W),
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|
.WUSER_EN(m_axi_wr[0].WUSER_EN),
|
|
.WUSER_W(m_axi_wr[0].WUSER_W),
|
|
.BUSER_EN(m_axi_wr[0].BUSER_EN),
|
|
.BUSER_W(m_axi_wr[0].BUSER_W)
|
|
) int_axi();
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|
|
|
// in-flight transaction count
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wire trans_start;
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wire trans_complete;
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localparam TR_CNT_W = $clog2(M_ISSUE_INT[n]+1);
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logic [TR_CNT_W-1:0] trans_count_reg = '0;
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|
|
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wire trans_limit = trans_count_reg >= TR_CNT_W'(M_ISSUE_INT[n]) && !trans_complete;
|
|
|
|
always_ff @(posedge clk) begin
|
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if (trans_start && !trans_complete) begin
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|
trans_count_reg <= trans_count_reg + 1;
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end else if (!trans_start && trans_complete) begin
|
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trans_count_reg <= trans_count_reg - 1;
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|
end
|
|
|
|
if (rst) begin
|
|
trans_count_reg <= 0;
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|
end
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|
end
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|
|
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// address arbitration
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logic [CL_S_COUNT_INT-1:0] w_select_reg = '0, w_select_next;
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logic w_select_valid_reg = 1'b0, w_select_valid_next;
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logic w_select_new_reg = 1'b0, w_select_new_next;
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|
|
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wire [S_COUNT-1:0] a_req;
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wire [S_COUNT-1:0] a_ack;
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wire [S_COUNT-1:0] a_grant;
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wire a_grant_valid;
|
|
wire [CL_S_COUNT_INT-1:0] a_grant_index;
|
|
|
|
if (S_COUNT > 1) begin : arb
|
|
|
|
taxi_arbiter #(
|
|
.PORTS(S_COUNT),
|
|
.ARB_ROUND_ROBIN(1),
|
|
.ARB_BLOCK(1),
|
|
.ARB_BLOCK_ACK(1),
|
|
.LSB_HIGH_PRIO(1)
|
|
)
|
|
a_arb_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.req(a_req),
|
|
.ack(a_ack),
|
|
.grant(a_grant),
|
|
.grant_valid(a_grant_valid),
|
|
.grant_index(a_grant_index)
|
|
);
|
|
|
|
end else begin
|
|
|
|
logic grant_valid_reg = 1'b0;
|
|
|
|
always @(posedge clk) begin
|
|
if (a_req) begin
|
|
grant_valid_reg <= 1'b1;
|
|
end
|
|
|
|
if (a_ack || rst) begin
|
|
grant_valid_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
assign a_grant_valid = grant_valid_reg;
|
|
assign a_grant = grant_valid_reg;
|
|
assign a_grant_index = '0;
|
|
|
|
end
|
|
|
|
// address mux
|
|
if (S_COUNT > 1) begin
|
|
assign int_axi.awid = {a_grant_index, int_s_axi_awid[a_grant_index]};
|
|
end else begin
|
|
assign int_axi.awid = int_s_axi_awid[a_grant_index];
|
|
end
|
|
assign int_axi.awaddr = AXI_M_ADDR_W'(int_s_axi_awaddr[a_grant_index]);
|
|
assign int_axi.awlen = int_s_axi_awlen[a_grant_index];
|
|
assign int_axi.awsize = int_s_axi_awsize[a_grant_index];
|
|
assign int_axi.awburst = int_s_axi_awburst[a_grant_index];
|
|
assign int_axi.awlock = int_s_axi_awlock[a_grant_index];
|
|
assign int_axi.awcache = int_s_axi_awcache[a_grant_index];
|
|
assign int_axi.awprot = int_s_axi_awprot[a_grant_index];
|
|
assign int_axi.awqos = int_s_axi_awqos[a_grant_index];
|
|
assign int_axi.awregion = int_s_axi_awregion[a_grant_index];
|
|
assign int_axi.awuser = int_s_axi_awuser[a_grant_index];
|
|
assign int_axi.awvalid = int_axi_awvalid[a_grant_index][n] && a_grant_valid;
|
|
|
|
always_comb begin
|
|
int_axi_awready[n] = '0;
|
|
int_axi_awready[n][a_grant_index] = a_grant_valid && int_axi.awready;
|
|
end
|
|
|
|
for (genvar m = 0; m < S_COUNT; m = m + 1) begin
|
|
assign a_req[m] = int_axi_awvalid[m][n] && !a_grant_valid && !trans_limit && !w_select_valid_next;
|
|
assign a_ack[m] = a_grant[m] && int_axi_awvalid[m][n] && int_axi.awready;
|
|
end
|
|
|
|
assign trans_start = int_axi.awvalid && int_axi.awready && a_grant_valid;
|
|
|
|
// write data mux
|
|
assign int_axi.wdata = int_s_axi_wdata[w_select_reg];
|
|
assign int_axi.wstrb = int_s_axi_wstrb[w_select_reg];
|
|
assign int_axi.wlast = int_s_axi_wlast[w_select_reg];
|
|
assign int_axi.wuser = int_s_axi_wuser[w_select_reg];
|
|
assign int_axi.wvalid = int_axi_wvalid[w_select_reg][n] && w_select_valid_reg;
|
|
|
|
always_comb begin
|
|
int_axi_wready[n] = '0;
|
|
int_axi_wready[n][w_select_reg] = w_select_valid_reg && int_axi.wready;
|
|
end
|
|
|
|
// write data routing
|
|
always_comb begin
|
|
w_select_next = w_select_reg;
|
|
w_select_valid_next = w_select_valid_reg && !(int_axi.wvalid && int_axi.wready && int_axi.wlast);
|
|
w_select_new_next = w_select_new_reg || a_grant_valid == 0 || a_ack != 0;
|
|
|
|
if (a_grant_valid && !w_select_valid_reg && w_select_new_reg) begin
|
|
w_select_next = a_grant_index;
|
|
w_select_valid_next = a_grant_valid;
|
|
w_select_new_next = 1'b0;
|
|
end
|
|
end
|
|
|
|
always_ff @(posedge clk) begin
|
|
w_select_reg <= w_select_next;
|
|
w_select_valid_reg <= w_select_valid_next;
|
|
w_select_new_reg <= w_select_new_next;
|
|
|
|
if (rst) begin
|
|
w_select_valid_reg <= 1'b0;
|
|
w_select_new_reg <= 1'b1;
|
|
end
|
|
end
|
|
|
|
// write response forwarding
|
|
wire [CL_S_COUNT_INT-1:0] b_select = CL_S_COUNT_INT'(int_axi.bid >> S_ID_W);
|
|
|
|
assign int_m_axi_bid[n] = int_axi.bid;
|
|
assign int_m_axi_bresp[n] = int_axi.bresp;
|
|
assign int_m_axi_buser[n] = int_axi.buser;
|
|
|
|
always_comb begin
|
|
int_axi_bvalid[n] = '0;
|
|
int_axi_bvalid[n][b_select] = int_axi.bvalid;
|
|
end
|
|
assign int_axi.bready = int_axi_bready[b_select][n];
|
|
|
|
assign trans_complete = int_axi.bvalid && int_axi.bready;
|
|
|
|
// M side register
|
|
taxi_axi_register_wr #(
|
|
.AW_REG_TYPE(M_AW_REG_TYPE[n*2 +: 2]),
|
|
.W_REG_TYPE(M_W_REG_TYPE[n*2 +: 2]),
|
|
.B_REG_TYPE(M_B_REG_TYPE[n*2 +: 2])
|
|
)
|
|
reg_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* AXI4 slave interface
|
|
*/
|
|
.s_axi_wr(int_axi),
|
|
|
|
/*
|
|
* AXI4 master interface
|
|
*/
|
|
.m_axi_wr(m_axi_wr[n])
|
|
);
|
|
|
|
end // m_ifaces
|
|
|
|
endmodule
|
|
|
|
`resetall
|