100 lines
1.8 KiB
Systemverilog
100 lines
1.8 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Zircon IP stack - TX ingress module
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*/
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module zircon_ip_tx_ingress #
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(
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parameter N_UI = 4,
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parameter UI_TX_FIFO_DEPTH = 32,
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parameter logic UI_TX_FIFO_EB_MODE = 1'b1
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* Client user interface
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*/
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input wire logic ui_clk,
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input wire logic ui_rst,
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taxi_axis_if.snk s_axis_ui_tx,
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taxi_axis_if.src m_axis_ui_tx_cpl,
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/*
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* Internal interfaces
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*/
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taxi_axis_if.src m_axis_pkt
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);
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localparam UI_DATA_W = s_axis_ui_tx.DATA_W;
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localparam DATA_W = m_axis_pkt.DATA_W;
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// TX FIFO
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taxi_axis_async_fifo #(
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.DEPTH(UI_TX_FIFO_EB_MODE ? (UI_DATA_W > DATA_W ? UI_DATA_W : DATA_W)/8*UI_TX_FIFO_DEPTH : UI_TX_FIFO_DEPTH),
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.RAM_PIPELINE(1),
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.OUTPUT_FIFO_EN(1'b0),
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.FRAME_FIFO(1'b0),
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.USER_BAD_FRAME_VALUE(1'b1),
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.USER_BAD_FRAME_MASK(1'b1),
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.DROP_OVERSIZE_FRAME(!UI_TX_FIFO_EB_MODE),
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.DROP_BAD_FRAME(!UI_TX_FIFO_EB_MODE),
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.DROP_WHEN_FULL(1'b0),
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.MARK_WHEN_FULL(1'b0),
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.PAUSE_EN(1'b0)
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)
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tx_fifo_inst (
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/*
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* AXI4-Stream input (sink)
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*/
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.s_clk(ui_clk),
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.s_rst(ui_rst),
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.s_axis(s_axis_ui_tx),
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/*
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* AXI4-Stream output (source)
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*/
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.m_clk(clk),
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.m_rst(rst),
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.m_axis(m_axis_pkt),
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/*
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* Pause
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*/
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.s_pause_req(1'b0),
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.s_pause_ack(),
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.m_pause_req(1'b0),
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.m_pause_ack(),
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/*
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* Status
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*/
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.s_status_depth(),
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.s_status_depth_commit(),
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.s_status_overflow(),
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.s_status_bad_frame(),
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.s_status_good_frame(),
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.m_status_depth(),
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.m_status_depth_commit(),
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.m_status_overflow(),
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.m_status_bad_frame(),
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.m_status_good_frame()
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);
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endmodule
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`resetall
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