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cbbad58efbf4ff971a97409514dd1c7244a02603
taxi-bsl/src/axi/rtl
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Alex Forencich cbbad58efb axi: Fix sideband signal handling in AXI lite crossbar 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-11-11 17:31:44 -08:00
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taxi_axi_adapter_rd.sv
axi: Add AXI width converter module and testbench
2025-08-30 21:10:08 -07:00
taxi_axi_adapter_wr.sv
axi: Add AXI width converter module and testbench
2025-08-30 21:10:08 -07:00
taxi_axi_adapter.f
axi: Add AXI width converter module and testbench
2025-08-30 21:10:08 -07:00
taxi_axi_adapter.sv
axi: Add AXI width converter module and testbench
2025-08-30 21:10:08 -07:00
taxi_axi_axil_adapter_rd.sv
axi: Add AXI to AXI lite adapter module and testbench
2025-08-30 21:11:20 -07:00
taxi_axi_axil_adapter_wr.sv
axi: Add AXI to AXI lite adapter module and testbench
2025-08-30 21:11:20 -07:00
taxi_axi_axil_adapter.f
axi: Add AXI to AXI lite adapter module and testbench
2025-08-30 21:11:20 -07:00
taxi_axi_axil_adapter.sv
axi: Add AXI to AXI lite adapter module and testbench
2025-08-30 21:11:20 -07:00
taxi_axi_fifo_rd.sv
Use logic instead of reg
2025-11-07 02:14:19 -08:00
taxi_axi_fifo_wr.sv
Use logic instead of reg
2025-11-07 02:14:19 -08:00
taxi_axi_fifo.f
axi: Add AXI FIFO module and testbench
2025-08-30 22:17:53 -07:00
taxi_axi_fifo.sv
axi: Add AXI FIFO module and testbench
2025-08-30 22:17:53 -07:00
taxi_axi_if.sv
axi: Add MAX_BURST_LEN and NARROW_BURST_EN parameters to AXI interface
2025-08-30 13:55:33 -07:00
taxi_axi_interconnect_rd.sv
axi: Dereference interface arrays in interconnect modules when extracting parameters
2025-11-11 14:32:50 -08:00
taxi_axi_interconnect_wr.sv
axi: Dereference interface arrays in interconnect modules when extracting parameters
2025-11-11 14:32:50 -08:00
taxi_axi_interconnect.f
axi: Add AXI interconnect module and testbench
2025-11-11 12:40:07 -08:00
taxi_axi_interconnect.sv
axi: Add AXI interconnect module and testbench
2025-11-11 12:40:07 -08:00
taxi_axi_ram.sv
axi: Tie off ruser/buser in AXI RAM module
2025-09-30 16:28:59 -07:00
taxi_axi_register_rd.sv
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_axi_register_wr.sv
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_axi_register.f
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_axi_register.sv
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_axil_adapter_rd.sv
axi: Add AXI lite width converter module and testbench
2025-08-30 13:02:27 -07:00
taxi_axil_adapter_wr.sv
axi: Add AXI lite width converter module and testbench
2025-08-30 13:02:27 -07:00
taxi_axil_adapter.f
axi: Add AXI lite width converter module and testbench
2025-08-30 13:02:27 -07:00
taxi_axil_adapter.sv
axi: Add AXI lite width converter module and testbench
2025-08-30 13:02:27 -07:00
taxi_axil_apb_adapter.sv
Clean up always blocks
2025-11-07 01:51:18 -08:00
taxi_axil_axi_adapter_rd.sv
axi: Add AXI lite to AXI adapter module and testbench
2025-08-30 13:40:43 -07:00
taxi_axil_axi_adapter_wr.sv
axi: Add AXI lite to AXI adapter module and testbench
2025-08-30 13:40:43 -07:00
taxi_axil_axi_adapter.f
axi: Add AXI lite to AXI adapter module and testbench
2025-08-30 13:40:43 -07:00
taxi_axil_axi_adapter.sv
axi: Add AXI lite to AXI adapter module and testbench
2025-08-30 13:40:43 -07:00
taxi_axil_crossbar_addr.sv
axi: Add AXI lite crossbar module and testbench
2025-11-11 15:06:32 -08:00
taxi_axil_crossbar_rd.f
axi: Add AXI lite crossbar module and testbench
2025-11-11 15:06:32 -08:00
taxi_axil_crossbar_rd.sv
axi: Fix sideband signal handling in AXI lite crossbar
2025-11-11 17:31:44 -08:00
taxi_axil_crossbar_wr.f
axi: Add AXI lite crossbar module and testbench
2025-11-11 15:06:32 -08:00
taxi_axil_crossbar_wr.sv
axi: Fix sideband signal handling in AXI lite crossbar
2025-11-11 17:31:44 -08:00
taxi_axil_crossbar.f
axi: Add AXI lite crossbar module and testbench
2025-11-11 15:06:32 -08:00
taxi_axil_crossbar.sv
axi: Add AXI lite crossbar module and testbench
2025-11-11 15:06:32 -08:00
taxi_axil_dp_ram.sv
axi: Tie off ruser/buser in AXI lite RAM modules
2025-09-30 16:30:32 -07:00
taxi_axil_if.sv
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_axil_interconnect_rd.sv
axi: Dereference interface arrays in interconnect modules when extracting parameters
2025-11-11 14:32:50 -08:00
taxi_axil_interconnect_wr.sv
axi: Dereference interface arrays in interconnect modules when extracting parameters
2025-11-11 14:32:50 -08:00
taxi_axil_interconnect.f
axi: Add AXI lite interconnect module and testbench
2025-11-11 10:20:26 -08:00
taxi_axil_interconnect.sv
axi: Add AXI lite interconnect module and testbench
2025-11-11 10:20:26 -08:00
taxi_axil_ram.sv
axi: Tie off ruser/buser in AXI lite RAM modules
2025-09-30 16:30:32 -07:00
taxi_axil_register_rd.sv
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_axil_register_wr.sv
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_axil_register.f
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_axil_register.sv
Reorganize repository
2025-05-18 12:25:59 -07:00